參數(shù)資料
型號(hào)： C5NPD0-DS
英文描述： QUAD BILATERAL SWITCH FOR TRANSMISSION OR MULTIPLEXING OF ANALOG OR DIGITAL SIGNALS
中文描述： 的C - 5網(wǎng)絡(luò)處理器的數(shù)據(jù)資料硅修訂D0
文件頁(yè)數(shù)： 69/100頁(yè)
文件大?。?/td> 2163K
代理商： C5NPD0-DS
Power Sequencing
69
MOTOROLA GENERAL BUSINESS INFORMATION
C5NPD0-DS/D REV 04
Each control input pin has a capacitance associated with it. The capacitance at the control
input is due to the package and the input circuitry connected to the pin. Capacitance is
based on these conditions: T
A
= 25
°
C
; V
DD33
= 3.3V; f = 1MHz.
Table 37
provides
capacitance data.
Power Sequencing
The VDD rail must be kept within 2.5V of the VDD33 rail. However, this rule can be violated
for periods up to one second, as is typical during power sequencing, as long as:
The VDD is not clamped to ground or some other low voltage.
The number of power cycling events averages to less than once per day over the
lifetime of the product.
It is intended that the VDD and VDD33 rail be sequenced to their final value together for
most applications.
It is also required that SCLK, SCLKX, TCLKI, PCLK, MDCLK, FTXCLK, and FRXCLK be running
or begin running during power sequencing to propagate reset inside the C-5 NP
Figure 9
indicates the relationship between the clocks and PRSTX. There is no requirement that the
asserting and deasserting edges of PRSTX be synchronous to the clocks. Reset must be
asserted within 100
μ
s of power initiation. Typically, reset is held low during power
initiation.
LVPECL Output Low Voltage
V
DD33
-1.810
V
DD33
-1.620
V
Load = 50ohm to
V
DD33
- 2V
LVPECL Input Current
-5
+5
μ
A
V
CPREF
V
DD33
-1.38
V
DD33
-1.26
Single-ended LVPECL
reference
*
All voltages are relative to Ground unless otherwise indicated.
Table 37
C-5 Network Processor Capacitance Data
PARAMETER
TYPICAL
MAX
UNIT
Input/Output Pins
7
8
pF
Input Pins
6
7
pF
Clock Pins
6
7
pF
Table 36
C-5 Network Processor DC Characteristics (continued) (continued)
PARAMETER*
MIN
MAX
UNIT
NOTES
F
n
.
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