參數(shù)資料
型號: C5NPD0-DS
英文描述: QUAD BILATERAL SWITCH FOR TRANSMISSION OR MULTIPLEXING OF ANALOG OR DIGITAL SIGNALS
中文描述: 的C - 5網(wǎng)絡(luò)處理器的數(shù)據(jù)資料硅修訂D0
文件頁數(shù): 40/100頁
文件大?。?/td> 2163K
代理商: C5NPD0-DS
40
CHAPTER 2: SIGNAL DESCRIPTIONS
C5NPD0-DS/D REV 04
MOTOROLA GENERAL BUSINESS INFORMATION
Serial Interface Signals
The Serial interface is a bidirectional two-wire serial bus. It can use one of the following
formats:
1
An 8bit data format followed by an acknowledge bit, which supports transfers at up to
400kbps (low speed).
2
a 16bit IEEE 802.3 MDIO data format with 10bits of addressing, which supports
transfers up to 25MHz (high speed).
The signals and pins are identical for both the high and low speed protocols.
Which of the two data rates used is selected by the state of the PROM interface
s SPLD
signal that is asserted while the PROM interface is idle. When SPLD is asserted
HI
the low
speed serial bus protocol is selected and when SPLD is asserted
LOW
the MDIO protocol is
selected.
The bus only supports a single master hierarchy that can operate as either a receiver or a
transmitter. The bus also supports collision detection and arbitration, and an integrated
addressing and data-transfer protocol.
Both SIDA and SICL are bidirectional lines that are connected, through a pull-up resistor,
to a positive supply voltage. When the bus is free, both lines are HIGH. The output stages
PSTOPX
K18
1
PCI
I/O
Target transaction stop request
PDEVSELX
N18
1
PCI
I/O
Target device selected
PPERRX
M18
1
PCI
I/O
Bus parity error
PSERRX
L18
1
PCI
I/O
System error
PCLK
L15
1
PCI
I
Bus clock
PRSTX
N17
1
PCI
I
Bus reset
PREQX
L17
1
PCI
O
Initiator bus request (arbitration)
PGNTX
N19
1
PCI
I
Initiator bus grant (arbitration)
PIDSEL
O18
1
PCI
I
Initialization device select
PINTA
O16
1
PCI
O
Interrupt
TOTAL PINS
50
Table 14
PCI Signals (continued)
SIGNAL NAME
PIN #
TOTAL
TYPE
I/O
SIGNAL DESCRIPTION
F
n
.
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