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參數(shù)資料
| 型號(hào)： | C5NPD0-DS |
| 英文描述： | QUAD BILATERAL SWITCH FOR TRANSMISSION OR MULTIPLEXING OF ANALOG OR DIGITAL SIGNALS |
| 中文描述： | 的C - 5網(wǎng)絡(luò)處理器的數(shù)據(jù)資料硅修訂D0 |
| 文件頁(yè)數(shù)： | 53/100頁(yè) |
| 文件大小： | 2163K |
| 代理商： | C5NPD0-DS |
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Signals Grouped by Pin Number
53
MOTOROLA GENERAL BUSINESS INFORMATION
C5NPD0-DS/D REV 04
During JTAG, SCLK and SCLKX must remain as differential inputs.
No Connection Pins
No connection pins are listed in
Table 29
.
Signals Grouped by Pin
Number
The C-5 NP signals are listed by pin number in
Table30
.
Table 28
Miscellaneous Test Signals For JTAG, Scan, and Internal Test Routines
SIGNAL NAME
PIN #
TOTAL
TYPE
SIGNAL DESCRIPTION
JTCK
T11
1
LVTTL
Test Clock
JTMS*
Z15
1
LVTTL
Test Mode Select. High selects modes
as defined in the IEEE 1149.1 JTAG
specification.
JTRSTX
X15
1
LVTTL
Test Reset (low active)
JTDI
AB15
1
LVTTL
Test Data In
JTDO
V15
1
LVTTL
Test Data Out
JHIGHZ
T12
1
LVTTL
Turns off all output drivers when High
JCLKBYP
T13
1
LVTTL
1X or 2X Clock Mode Select. Low
selects 1X, High selects 2X.
JSE
S12
1
LVTTL
Scan Enable. High enables scan test.
JS00-JS09
L12, N13, N12, P13, P12, Q12, R13, R12,
R11, R10
10
LVTTL
Scan Out Pins
TOTAL PINS
18
*
According to the IEEE 1149.1 specification, the JTMS, JTRST, and JTDI pins must have internal pullups. While the C-5 NP does not currently have pads
with pullups, customers can pull up these three pins on the board.
Table 29
No Connection Pins
SIGNAL NAME
PIN #
TOTAL
TYPE
SIGNAL DESCRIPTION
NC1 - NC11
I18, H17, H18, N10, P10, N11, P11, U14,
V14, U16, V16
11
nc
Reserved for future functionality
TOTAL PINS
11
F
n
.
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