參數(shù)資料
型號(hào)： C5NPD0-DS
英文描述： QUAD BILATERAL SWITCH FOR TRANSMISSION OR MULTIPLEXING OF ANALOG OR DIGITAL SIGNALS
中文描述： 的C - 5網(wǎng)絡(luò)處理器的數(shù)據(jù)資料硅修訂D0
文件頁(yè)數(shù)： 49/100頁(yè)
文件大?。?/td> 2163K
代理商： C5NPD0-DS
Pin Descriptions Grouped by Function
49
MOTOROLA GENERAL BUSINESS INFORMATION
C5NPD0-DS/D REV 04
TLU SRAM Interface
Signals
The TLU SRAM interface supports up to 32MBytes of SRAM at frequencies to 133MHz
using LVTTL signaling levels (in single bank-mode only) and SRAM technologies up to
64Mbits. The TLU SRAM interface signals are described in
Table 24
.
MDCLK
J17
1
LVTTL
I
Clock: MDCLK is driven by the system clock. All
SDRAM input signals are sampled on the positive
edge of the MDCLK. MDCLK also increments the
internal burst counter and controls the output
registers.
TOTAL PINS
161
Table 23
BMU SDRAM Interface Signals (continued)
SIGNAL NAME
PIN #
TOTAL
TYPE
I/O
SIGNAL DESCRIPTION
Table 24
TLU SRAM Interface Signals
SIGNAL NAME
PIN #
TOTAL
TYPE
I/O
SIGNAL DESCRIPTION
TD0 - TD63
N1, L1, J1, H1, M2, K2, I2, G2, N2, L2, J2, H2, L3, J3,
H3, G4, 04, M4, K4, I4, L4, J4, H4, G6, N5, L5, J5, H5,
N6, L6, I6, H6, K6, J6, M6, H7, L7, J7, H8, N8, M8, K8,
I8, G8, N7, L8, J8, H9, L9, J9, J10, G10, P9, O8, L10,
H10, O10, N9, L11, I10, M10, K10, J11, H11
64
LVTTL
I/O
TLU Memory Data
TA0 - TA21
R1, P1, S2, Q2, O2, R2, P2, R3, P3, N3, S4, Q4, R4, P4,
N4, R5, P5, S6, R6, Q6, P6, O6
22
LVTTL
O
TLU Memory Address
TA18x - TA21x
T8, Q8, R7, P7
4
LVTTL
O
Data Parity
TCE0X - TCE3X
P8, R8, S8, T9
4
LVTTL
O
TLU Memory Chip Enable
TWE0X - TWE3X
Q10, R9, S10, T10
4
LVTTL
O
TLU Memory Write Enable
TCLKI
M12
1
LVTTL
I
TLU Clock Input
TOTAL PINS
99
Table 25
Memory Bank Selection
CHIP SELECT (SIGNALS TA18X THROUGH TA21X)
SIZE
BANK 1
BANK 2
BANK 3
BANK 4
CE2
CE2X
CE2
CE2X
CE2
CE2X
CE2
CE2X
4Mbit
TA18x
TA19
TA18
TA19
TA18x
TA19x
TA18
TA19x
8Mbit
TA19x
TA20
TA19
TA20
TA19x
TA20x
TA19
TA20x
16Mbit
TA20x
TA21
TA20
TA21
TA20x
TA21x
TA20
TA21x
F
n
.
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