參數(shù)資料
型號(hào)： C5NPD0-DS
英文描述： QUAD BILATERAL SWITCH FOR TRANSMISSION OR MULTIPLEXING OF ANALOG OR DIGITAL SIGNALS
中文描述： 的C - 5網(wǎng)絡(luò)處理器的數(shù)據(jù)資料硅修訂D0
文件頁數(shù)： 30/100頁
文件大?。?/td> 2163K
代理商： C5NPD0-DS
30
CHAPTER 2: SIGNAL DESCRIPTIONS
C5NPD0-DS/D REV 04
MOTOROLA GENERAL BUSINESS INFORMATION
CP Interface Signals
The C-5 NP
’
s 16 CPs support various network physical interfaces, providing a serial
interface to the PHY layer. Interfaces are configured via bits in the C-5 NP register set.
Many interfaces are possible by programming the configuration registers. CPs can be
used individually or in a cluster (four CPs) to implement the various interfaces.
Table 6
provides a quick reference of all the CP pins organized by clusters. There are seven
physical I/O pins associated with each CP All pins are capable of receiving data, with some
configurable to be input clocks, output clocks, or data drivers. In addition, pairs of pins can
be configured as differential pairs for LVPECL compatibility.
In the case of RMII, OC-3, DS1, and DS3, the drivers and receivers at the pin are locally
configured to match the relevant PHY or Framer chip. OC-12 uses the aggregation of four
CPs (one cluster), while GMII and Ten Bit Interface (TBI) can use either eight CPs (four for
receive and four for transmit) or four CPs that share the transmit and receive functions for
non-wire speed applications.
During CP aggregation, all 28 pins associated with a cluster are routed to all of the Serial
Data Processors (SDPs) in that cluster. This allows round-robin usage of portions of the
SDPs, with each getting access to the necessary I/O pins.
The signals for the following CP physical interfaces are included in this section:
DS1/T1 Framer Interface Configuration
10/100 Ethernet (RMII) Configuration
Gigabit Ethernet (GMII) Configuration
CPREF
L13
1
LVPECL
I
Reference
TOTAL
11
*
SCLK and SCLKX must not be AC-coupled.
The frequencies specified for CCLK0 - CCLK7 allow full flexibility for the C-5 NP. Clock inputs associated with a
specific protocol should be wired to ground when that protocol is not used by the C-5 NP. It is also possible
to use one or more CCLK
n
inputs for other frequencies. Contact your C-Port representative for more
information.
If any of the CPs are configured for LVPECL operation (OC3) using the pin mode registers, then CPREF must
be wired to an external reference, as specified in
Table 36
on page 68. If none of the CPs are configured for
LVPECL operation, then the CPREF pin can be left unconnected. It is acceptable to tie the CPREF pin high or
low through a resistor, or into the specified reference, but this is not required.
Table 5
Clock and Reference Signals (continued)
SIGNAL NAME
PIN #
TOTAL
TYPE
I/O
SIGNAL DESCRIPTION
F
n
.
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