參數(shù)資料
型號(hào)： C5NPD0-DS
英文描述： QUAD BILATERAL SWITCH FOR TRANSMISSION OR MULTIPLEXING OF ANALOG OR DIGITAL SIGNALS
中文描述： 的C - 5網(wǎng)絡(luò)處理器的數(shù)據(jù)資料硅修訂D0
文件頁數(shù)： 24/100頁
文件大?。?/td> 2163K
代理商： C5NPD0-DS
24
CHAPTER 1: FUNCTIONAL DESCRIPTION
C5NPD0-DS/D REV 04
MOTOROLA GENERAL BUSINESS INFORMATION
or cells from the C-5 NP to a hardware interface that provides connectivity to other
network processors or other similar line processing hardware. There are numerous
parameters that can be configured within the FP to allow the interface to be adapted to
different fabric protocols. The FP is Utopia-1, 2 and Utopia-3, IBM PRIZMA, and PowerX
(Csix-L0) compatible.
The FP can be configured to run at any frequency up to 110MHz, and the receive and
transmit data buses are 16 or 32 bits wide. This allows a wide range of supported
bandwidths to and from the switching fabric, all the way up to 3200Mbps full duplex
bandwidth.
Buffer Management Unit
The Buffer Management Unit (BMU) interfaces the C-5 NP to external pipeline
architecture, Single Data Rate Synchronous DRAM. The external memory is partitioned
and used as buffers for receiving and transmitting data between CPs, the FP and the XP It
is also used as second level storage in the XP memory hierarchy.
The interface to an array of SDRAM chips is 139bits wide, composed of 128 data bits, two
internal control bits, and nine SECDED (single error correction-double error detection) ECC
(error correction code) bits. The interface is compliant with the PC100 standard and
operates at up to 125MHz with 3.3V LVTTL-compatible inputs and outputs. The refresh
period, Trcd, Tcas, Trp, Tmrd, and Trc are configurable via boot time configuration (see the
C-5 Network Processor Architecture Guide
for more details).
The C-5 NP uses auto-refresh mode and the interface, (which is not configurable),
transfers four bits of data for each read and write using a sequential burst type.
Some of these parameters are programmed into the SDRAMs
’
mode register and can be
applied only once per power cycle. The ECC functionality can be enabled or disabled via
configuration register writes.
If needed, the interface can narrowed to 128bits by disabling ECC and providing board
pull-ups for the two control bits and nine ECC bits. This is useful if DIMMs are used in the
board design. If individual SDRAM parts are used, x16 and x32 are supported. The BMU
supports SDRAM devices that use 12 address lines. Internal address calculation paths limit
the maximum memory size to 128MBytes. Only one physical bank of SDRAM is supported.
Table Lookup Unit
The Table Lookup Unit (TLU) performs table lookups in external SRAM. It can also be used
for statistics accumulation and retrieval and as general data storage. The TLU
F
n
.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
C5NP-PB 制造商:未知廠家 制造商全稱:未知廠家 功能描述:C-5 Network Processor Fact Sheet
C5P-0 制造商:Wieland Electric Inc 功能描述:
C5P0108N-R10 制造商:ELECTROSWITCH ELECTRONIC PRODUCTS 功能描述:
C5P0112N-A 功能描述:旋鈕開關(guān) 02-12POS/1P/1SECTION RoHS:否 制造商:C&K Components 位置數(shù)量:5 卡片組數(shù)量: 每卡片組極數(shù):2 電流額定值:250 mA 電壓額定值:125 V 指數(shù)角: 觸點(diǎn)類型: 觸點(diǎn)形式:DPST 端接類型:Solder 安裝類型:Panel 觸點(diǎn)電鍍:Silver
C5P0112N-RA 功能描述:SWITCH ROTARY SP-12POS ENCLOSED RoHS:是 類別:開關(guān) >> 旋轉(zhuǎn) 系列:C5 RoHS指令信息:435123-1 Statement of Compliance 產(chǎn)品目錄繪圖:Rotary Switch 特色產(chǎn)品:TE Connectivity Switches 3D 型號(hào):435123-1.pdf 標(biāo)準(zhǔn)包裝:1 系列:6000 位置數(shù):10 層數(shù):1 每層電極數(shù):- 每層電路:BCD 觸點(diǎn)額定電壓:0.125A @ 115VAC 觸動(dòng)器類型:旋鈕 安裝類型:PCB，通孔 端接類型:PC 引腳 方向:垂直 擺角:36° 產(chǎn)品目錄頁面:2570 (CN2011-ZH PDF) 其它名稱:435123-1-ND450-1183A26201A26201-ND
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