參數(shù)資料
型號(hào): C5NPD0-DS
英文描述: QUAD BILATERAL SWITCH FOR TRANSMISSION OR MULTIPLEXING OF ANALOG OR DIGITAL SIGNALS
中文描述: 的C - 5網(wǎng)絡(luò)處理器的數(shù)據(jù)資料硅修訂D0
文件頁數(shù): 43/100頁
文件大?。?/td> 2163K
代理商: C5NPD0-DS
Pin Descriptions Grouped by Function
43
MOTOROLA GENERAL BUSINESS INFORMATION
C5NPD0-DS/D REV 04
7
SPLD is asserted for one SPCLK cycle, loading the first PROM_DATA into the network
processor PROM_RETURN_DATA register and the second PROM_DATA into the
external shift register.
8
SPLD is deasserted for 22 SPCLK cycles, shifting the second PROM_DATA into the
network processor internal shift register.
9
SPLD is asserted for one SPCLK cycle, loading the second PROM_DATA into the
network processor PROM_RETURN_DATA register.
Figure 5
PROM Interface Timing Outline
General System Interface Signal
Table 17
provides the signal for the Executive Processor reset power status and I/O clock.
The C-5 NP can be powered up with the XP either running or with the XP in reset mode
similar to the CPs. When the XP remains in reset mode, an external host can be used to
control the initialization of the C-5 NP
SPCLK
SPLD
1
2
4
5
6
7
8
9
11
10
12 13 14 15 16 17 18 19 20 21 22 23 1
2
3
4
5
6
7
8
9
10 11
12 13 14 15 16 17 18 19 20 21 22 23 1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
20
19
21 22 23 1
2
3
4
5
6
7
x
A
20
A
19
The PROM_ADDR is loaded into the
The PROM_ADDR is shifted into
(SPCLK Rising Edge used for shifting)
2
A
18
SPDTO
A
17
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
CE
The PROM_ADDR is loaded into the
external presentation register.
The PROM_DATA is
The PROM_DATA is loaded into the
external shift register.
The PROM_DATA is shifted into the C-5’s
Internal shift register.
The PROM_DATA is loaded into the C-5’s
internal PROM_RETURN_DATA register.
SPDTI
x
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
x
x
x
x
x
x
XP PROM Interface outline
XP PROM Interface detail
SPLD
SPDTO
SPDTI
A1
A2
A3
A4
A5
D1
D2
D3
D1
D2
A1
A2
A3
A4
1
3
4
5
6
7
8
9
F
n
.
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