參數(shù)資料
型號(hào): ATA6285N-PNPW
廠商: ATMEL CORP
元件分類: 通信及網(wǎng)絡(luò)
英文描述: SPECIALTY TELECOM CIRCUIT, QCC32
封裝: 5 X 5MM, QFN-32
文件頁數(shù): 85/121頁
文件大?。?/td> 9917K
代理商: ATA6285N-PNPW
66
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
T3I/PCINT17 - Port D, Bit 1
T3I: External input clock for Timer1, Timer2 or Timer3.
The pin has to be configured as an input (DDD1 set (zero)) to serve this function.
PCINT17, Pin Change Interrupt Source 17: The PD1 pin can serve as an external interrupt
source.
T2ICP/PCINT16 - Port D, Bit 0
T2ICP - Timer2 Input Capture pin: The PD0 pin can act as an external Input Capture pin for
Timer/Counter2. The pin has to be configured as an input (DDD0 set (zero)) to serve this
function.
PCINT16, Pin Change Interrupt Source 16: The PD0 pin can serve as an external interrupt
source.
Table 3-28 and Table 3-29 relates the alternate functions of Port D to the overriding signals
Table 3-28.
Overriding Signals for Alternate Functions in PD7..PD4
Signal Name PD7/SDIN/PCINT23
PD6/T2O2/PCINT15
PD5/T2O1/PCINT14
PD4/ECIN1/PCINT13
PUOE
0
PUOV
0
DDOE
SPI (T2M[3..0] =
0b1001)
00
CMM[1..0]
× ECINS ×
CSS
DDOV
0
PVOE
0
T2O2 ENABLE
T2O1 ENABLE
0
PVOV
0
T2O2
T2O1
0
DIEOE
PCINT23
× PCIE2
PCINT22
× PCIE2
PCINT21
× PCIE2
PCINT20
× PCIE2
DIEOV
1
DI
PCINT23 INPUT
SDIN INPUT
PCINT22 INPUT
PCINT21 INPUT
PCINT20 INPUT
ECIN1 INPUT
AIO
Table 3-29.
Overriding Signals for Alternate Functions in PD3..PD0
Signal Name
PD3/INT1/PCINT19
PD2/INT0/PCINT18
PD1/T3I/PCINT17
PD0/T2ICP/PCINT16
PUOE
0
PUOV
0
DDOE
0
DDOV
0
PVOE
0
PVOV
0
DIEOE
PCINT19
× PCIE2 +
INT1 ENABLE
PCINT18
× PCIE2 +
INT0 ENABLE
PCINT17
× PCIE2
PCINT16
× PCIE2
DIEOV
1
DI
PCINT19 INPUT INT1
INPUT
PCINT18 INPUT INT0
INPUT
PCINT17 INPUT
T3I INPUT
PCINT16 INPUT
T2ICP INPUT
AIO
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