參數(shù)資料
型號: ATA6285N-PNPW
廠商: ATMEL CORP
元件分類: 通信及網(wǎng)絡
英文描述: SPECIALTY TELECOM CIRCUIT, QCC32
封裝: 5 X 5MM, QFN-32
文件頁數(shù): 22/121頁
文件大?。?/td> 9917K
代理商: ATA6285N-PNPW
12
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
Six of the 32 registers can be used as three 16-bit indirect address-register pointers for Data
Space addressing - enabling efficient address calculations. One of these address pointers can
also be used as an address pointer to look up tables in Flash program memory. These added
function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and
a register. Single register operations can also be executed in the ALU. After an arithmetic opera-
tion, the Status Register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to
address directly the whole address space. Most Atmel
AVR instructions have a single 16-bit
word format. Every program memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section and the
Application Program section. Both sections have dedicated Lock bits for write and read/write
protection. The SPM instruction (Store Program Memory instruction) that writes into the Applica-
tion Flash memory section must reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the
Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack
size is only limited by the total SRAM size and the usage of the SRAM. All user programs must
initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack
Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed
through the five different addressing modes supported in the Atmel AVR architecture.
The memory spaces in the Atmel AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global
Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the
Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector posi-
tion. The lower the Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-
ters, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data
Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATA6289 has
Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD
instructions can be used.
3.5.2
ALU - Arithmetic Logic Unit
The high-performance Atmel AVR ALU operates in direct connection with all the 32 general pur-
pose working registers. Within a single clock cycle, arithmetic operations between general
purpose registers or between a register and an immediate are executed. The ALU operations
are divided into three main categories - arithmetic, logical, and bit-functions. Some implementa-
tions of the architecture also provide a powerful multiplier supporting both signed/unsigned
multiplication and fractional format. See the Section 3.22 “Instruction Set Summary” on page
184 for a detailed description.
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