參數(shù)資料
型號: ATA6285N-PNPW
廠商: ATMEL CORP
元件分類: 通信及網(wǎng)絡
英文描述: SPECIALTY TELECOM CIRCUIT, QCC32
封裝: 5 X 5MM, QFN-32
文件頁數(shù): 28/121頁
文件大?。?/td> 9917K
代理商: ATA6285N-PNPW
14
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
Bit 1 - Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See Section 3.22
Bit 0 - C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See Section 3.22 “Instruc-
tion Set Summary” on page 184 for detailed information.
3.5.4
General Purpose Register File
The Register File is optimized for the Atmel
AVR Enhanced RISC instruction set. In order to
achieve the required performance and flexibility, the following input/output schemes are sup-
ported by the Register File:
One 8-bit output operand and one 8-bit result input
Two 8-bit output operands and one 8-bit result input
Two 8-bit output operands and one 16-bit result input
One 16-bit output operand and one 16-bit result input
Figure 3-3 shows the structure of the 32 general purpose working registers in the CPU.
Figure 3-3.
Atmel AVR CPU General Purpose Working Registers
Most of the instructions operating on the Register File have direct access to all registers, and
most of them are single cycle instructions.
As shown in Figure 3-3, each register is also assigned a data memory address, mapping them
directly into the first 32 locations of the user Data Space. Although not being physically imple-
mented as SRAM locations, this memory organization provides great flexibility in access of the
registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.
Bit:
7
0
Addr.
R0
0x00
R1
0x01
R2
0x02
R13
0x0D
General
R14
0x0E
Purpose
R15
0x0F
Working
R16
0x10
Registers
R17
0x11
R26
0x1A
X-register low byte
R27
0x1B
X-register high byte
R28
0x1C
Y-register low byte
R29
0x1D
Y-register high byte
R30
0x1E
Z-register low byte
R31
0x1F
Z-register high byte
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相關代理商/技術參數(shù)
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