參數(shù)資料
型號: ATA6285N-PNPW
廠商: ATMEL CORP
元件分類: 通信及網(wǎng)絡(luò)
英文描述: SPECIALTY TELECOM CIRCUIT, QCC32
封裝: 5 X 5MM, QFN-32
文件頁數(shù): 59/121頁
文件大?。?/td> 9917K
代理商: ATA6285N-PNPW
42
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
Figure 3-15. Reset Logic
3.9.2.1
Power-on Reset
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level
is defined in Table 3-13. The POR is activated whenever V
CC is below the detection level
V
POT(rising). The POR circuit can be used to trigger the start-up Reset, as well as to detect a fail-
ure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the
Power-on Reset threshold voltage V
POT(rising) invokes the delay counter, which determines how
long the device is kept in internal RESET after V
CC rise. The internal RESET - signal is activated
again, without any delay, when V
CC decreases below the detection level VPOT(falling).
Power-on
Reset Circuit
BORF
WDRF
T
S
RF
EXTRF
PORF
DATA BUS
MCU Status
Register (MCUSR)
Brown-out
Reset Circuit
Watchdog
Timer
Watchdog
Timer
Reset
Reset Circuit
INTERNAL
RESET
Spike
Filter
SRC Oscillator
FRC Oscillator
Delay Counters
TIMEOUT
COUNTER
RE
S
ET
R
Q
S
VCC
BODLS
Table 3-13.
Reset Characteristics
Parameters
Symbol
Min.
Typ.
Max.
Unit
Power-on Reset threshold voltage (rising)
VPOT
-1.15
-
V
Power-on Reset threshold voltage (falling)
-
1.15
-
V
RESET pin threshold voltage
VRST
0.2VCC
-
0.8xVCC
V
Minimum pulse width on RESET pin
tRST
2-
-
s
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