參數(shù)資料
型號: ATA6285N-PNPW
廠商: ATMEL CORP
元件分類: 通信及網(wǎng)絡(luò)
英文描述: SPECIALTY TELECOM CIRCUIT, QCC32
封裝: 5 X 5MM, QFN-32
文件頁數(shù): 110/121頁
文件大?。?/td> 9917K
代理商: ATA6285N-PNPW
89
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.13.5.8
Timer2 Control Register B – T2CRB
Bits 7..1 - Res: Reserved Bits
These bits are reserved bits in the ATA6289 and will always read as zero.
Bit 0 - T2SCE: Timer2 Software Capture Enable Bit
The T2SCE bit must be written to logic one to generate a software capture event. The T2SCE bit
is cleared after the counter value is saved in the capture register. The Timer2 counter value is
readable via its capture register during run time.
3.13.5.9
Timer2 Modulator Data Register – T2MDR
The modulator Transmit Data Buffer Register and the modulator Receive Data Buffer Register
shares the same I/O address labeled as modulator Data Register or T2MDR. The Transmit Data
Buffer Register (TXB) will be the destination for the data written to the T2MDR Register location.
Reading the T2MDR Register location will return the contents of the Receive Data Buffer Regis-
ter (RXB).
3.13.5.10
Timer2 Input Capture Register – T2ICR
The Input Capture Register is updated with the counter value (T2CNT) each time an event
occurs on the T2ICP pin, or Timer1 output clock CLK
T1, or after a software capture event is gen-
erated with the T2SCE bit.
The Input Capture Register is a 16-bit register. To ensure that both the high and low bytes are
read simultaneously when the CPU accesses these registers, the access is performed using an
8-bit temporary High Byte Register (TEMP). This temporary register is shared by all 16-bit regis-
Bit
7
654
32
10
-
T2SCE
T2CRB
Read/Write
RR
R
R/W
Initial Value
0
000
00
Bit
76
54
32
10
T2MDR [7..0]
T2MDR (read)
T2MDR [7..0]
T2MDR (write)
Read/Write
R/W
Initial Value
00
Bit
76
54
32
10
T2ICRH [15..8]
T2ICRH
T2ICRL [7..0]
T2ICRL
Read/Write
RR
Initial Value
00
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