參數(shù)資料
型號: ATA6285N-PNPW
廠商: ATMEL CORP
元件分類: 通信及網(wǎng)絡(luò)
英文描述: SPECIALTY TELECOM CIRCUIT, QCC32
封裝: 5 X 5MM, QFN-32
文件頁數(shù): 72/121頁
文件大小: 9917K
代理商: ATA6285N-PNPW
54
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.12
I/O-Ports
3.12.1
Introduction
All Atmel
AVR ports have true Read-Modify-Write functionality when used as general digital
I/O ports. This means that the direction of one port pin can be changed without unintentionally
changing the direction of any other pin with the SBI and CBI instructions. The same applies
when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if
configured as input). Each output buffer has symmetrical drive characteristics with both high sink
and source capability. The pin driver is strong enough to drive LED displays directly. All port pins
have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O
pins have protection diodes to both V
CC and Ground as indicated in Figure 3-21. Refer to Sec-
electrical parameters.
Figure 3-21. I/O Pin Equivalent Schematic
All registers and bit references in this section are written in general form. A lower case “x” repre-
sents the numbering letter for the port, and a lower case “n” represents the bit number. However,
when using the register or bit defines in a program, the precise form must be used. For example,
PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Regis-
Three I/O memory address locations are allocated for each port, one each for the Data Register
- PORTx, Data Direction Register - DDRx, and the Port Input Pins - PINx. The Port Input Pins
I/O location is read only, while the Data Register and the Data Direction Register are read/write.
However, writing a logic one to a bit in the PINx Register, will result in a toggle in the correspond-
ing bit in the Data Register. In addition, the Pull-up Disable - PUD bit in MCUCR disables the
pull-up function for all pins in all ports when set.
Using the I/O port as General Digital I/O is described in Section 3.12.2 “Ports as General Digital
I/O” on page 55. Most port pins are multiplexed with alternate functions for the peripheral fea-
tures on the device. How each alternate function interferes with the port pin is described in
Section 3.12.3 “Alternate Port Functions” on page 59. Refer to the individual module sections for
a full description of the alternate functions.
Note that enabling the alternate function of some of the port pins does not affect the use of the
other pins in the port as general digital I/O.
Cpin
Rpu
VBAT
Pxn
Control
Logic
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