參數(shù)資料
型號： ATA6285N-PNPW
廠商： ATMEL CORP
元件分類： 通信及網(wǎng)絡(luò)
英文描述： SPECIALTY TELECOM CIRCUIT, QCC32
封裝： 5 X 5MM, QFN-32
文件頁數(shù)： 69/121頁
文件大?。?/td> 9917K
代理商： ATA6285N-PNPW
51
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.11.2
External Interrupt Mask Register – EIMSK
Bits 7..2 - Res: Reserved Bits
These bits are reserved bits at the ATA6289 and will always read as zero.
Bit 1 - INT1: External INTerrupt Request 1 Enable
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-
nal pin interrupt is enabled. The Interrupt Sense Control 1 bits ISC11 and ISC10 in the External
Interrupt Control Register A (EICRA) define whether the external interrupt is activated on rising
and/or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt
request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt
Request 1 is executed from the INT1 Interrupt Vector.
Bit 0 - INT0: External INTerrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-
nal pin interrupt is enabled. The Interrupt Sense Control 0 bits ISC01 and ISC00 in the External
Interrupt Control Register A (EICRA) define whether the external interrupt is activated on rising
and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt
request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt
Request 0 is executed from the INT0 Interrupt Vector.
3.11.3
External Interrupt Flag Register – EIFR
Bits 7..2 - Res: Reserved Bits
These bits are reserved bits at the ATA6289 and will always read as zero.
Bit 1 - INTF1: External INTerrupt Flag 1
When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 becomes set
(one). If the I-bit in SREG and the INT1 bit in EIMSK are set (one), the MCU will jump to the cor-
responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared
when INT1 is configured as a level interrupt.
Bit 0 - INTF0: External INTerrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set
(one). If the I-bit in SREG and the INT0 bit in EIMSK are set (one), the MCU will jump to the cor-
responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared
when INT0 is configured as a level interrupt.
Bit
765
4321
0
-
INT1
INT0
EIMSK
Read/Write
R
RRRR
R
R/W
Initial Value
000
0000
0
Bit
7
654
32
10
-
INTF1
INTF0
EIFR
Read/Write
RR
R/W
Initial Value
0
000
00
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ATA6285N-PNQW 功能描述:射頻微控制器 - MCU IC LF, Cap. Sens. Interface RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:Si100x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:24 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LGA-42 安裝風格:SMD/SMT 封裝:Tube
ATA6285-PNPW 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:TPMS Control and Transmitter IC
ATA6285-PNQW 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:TPMS Control and Transmitter IC
ATA6286 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:TPMS Control and Transmitter IC
ATA6286C-PNPW 制造商:Atmel Corporation 功能描述:IC CTLR/XMITTER 433MHZ 32QFN 制造商:Atmel Corporation 功能描述:Active RFID AVR-uC, 125kHz + 433MHz
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