參數(shù)資料
型號： ATA6285N-PNPW
廠商： ATMEL CORP
元件分類： 通信及網(wǎng)絡(luò)
英文描述： SPECIALTY TELECOM CIRCUIT, QCC32
封裝： 5 X 5MM, QFN-32
文件頁數(shù)： 5/121頁
文件大?。?/td> 9917K
代理商： ATA6285N-PNPW
102
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
The two Compare Registers (T3CORA, T3CORB) and the Capture Register (T3ICR) are all
16-bit registers. Special procedures must be followed when accessing the 16-bit registers.
These procedures are described in Section 3.13.2 “Accessing 16-bit Registers” on page 70. The
Timer3 control, mode, mask and flag registers (T3CRA, T3CRB, T3MRA, T3MRB, T3IMR,
T3IFR) are all 8-bit registers and have no CPU access restrictions.
The comparator outputs are controlled by a control register (T3CRB) and contain mask bits for
the actions (counter reset, output toggle, single action) which can be triggered by a compare
match event or a capture event. The Output Compare Registers (T3CORA, T3CORB) are com-
pared with the Timer3/Counter3 value at every time. The counter can also be enabled to
execute single actions with one or both compare registers. If this mode is set the corresponding
compare match event is generated once a time after the counter starts.
The timer uses its compare registers alternately, if the T3AC bit is set at the T3CRA register.
After the timer has been activated, the first comparison is execute by the compare register A, the
second is execute by the compare register B, the third is execute by the compare register A and
so on as shown in Figure 3-48. This makes it easy to generate signals with constant periods and
variable duty cycle or to generate signals with variable pulse and space widths. If the T3AC bit is
cleared at the T3CRA register, the timer uses its compare registers not alternately for compare
matches.
Figure 3-48. Timer3 Alternate Compare Register Matches
This architecture enables the timer for various modes. The Timer3 operation modes and also the
modulator Output pin (T3O) is controlled by the T3MRB register.
Interrupt requests (shorten as Int. Req.) signals are all visible in the Timer Interrupt Flag Register
(T3IFR). All interrupts are individually masked with the Timer Interrupt Mask register (T3IMR).
The counter3 input clock (CL3) can be supplied via the I/O Clock (CLK
I/O), the external input
clock (T2I), the external input clock (T3I), the Timer0 output clock (CLK
T0), the Timer1 output
clock (CLK
T1), the Timer2 output clock (CLKT2), the integrated SRC output signal (SCH), or the
Timer clock (CLT).
T3CORA
inactive
T3CORB
active
Start (T3E)
or
Restart
T3CORA
active
Compare match
T3CORB
inactive
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ATA6285N-PNQW 功能描述:射頻微控制器 - MCU IC LF, Cap. Sens. Interface RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:Si100x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:24 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LGA-42 安裝風(fēng)格:SMD/SMT 封裝:Tube
ATA6285-PNPW 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:TPMS Control and Transmitter IC
ATA6285-PNQW 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:TPMS Control and Transmitter IC
ATA6286 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:TPMS Control and Transmitter IC
ATA6286C-PNPW 制造商:Atmel Corporation 功能描述:IC CTLR/XMITTER 433MHZ 32QFN 制造商:Atmel Corporation 功能描述:Active RFID AVR-uC, 125kHz + 433MHz
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