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| 型號(hào)： | AD1801 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Single-Chip Fax/Data/ Voice Modem(單片的傳真/數(shù)據(jù)/語(yǔ)音調(diào)制解調(diào)器) |
| 中文描述： | 單芯片傳真/數(shù)據(jù)/語(yǔ)音調(diào)制解調(diào)器（單片的傳真/數(shù)據(jù)/語(yǔ)音調(diào)制解調(diào)器） |
| 文件頁(yè)數(shù)： | 46/52頁(yè) |
| 文件大?。?/td> | 348K |
| 代理商： | AD1801 |
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AD1801
–46–
REV. 0
START-UP SEQUENCE
The following paragraphs describe a typical, generic start-up
sequence for the purpose of helping hardware, systems and
software driver engineers understand some of the considerations
involved in bringing up a system that includes the AD1801.
Note that it does not exhaustively outline all of the flexible
configurations and features available in the AD1801.
1. System power supplies stabilize.
2. Assert the RESET and/or
RESET
signals.
3. Deassert the RESET and/or
RESET
signals.
4. Power up the codecs. Write “1” to the CEN (Codec Enable)
bit in the Codec Configuration register. This will initiate the
process of powering up the AD1801 codecs (DAA codec,
handset codec and monitor speaker DAC). Poll this bit until
the readback value is “1,” which indicates that the codec
power-up process is complete.
The time required to power up the codec from the powered
down state (not from cold start) depends on the state of the
SBEN (Standby Enable) bit in the Codec Configuration
register. Codec power-up will take either 500 ms (SBEN =
0) or 15 ms (SBEN = 1). When SBEN is set to “1,” the
analog voltage reference is not powered down, so power-up
is faster at the expense of higher power consumption in the
powered down state.
5. Power up the individual codec channels.
Write “1” to the MEN (Modem Enable) bit in the Codec
Configuration register to power up the modem (DAA) codec
channel (ADC and DAC). Power-up of the modem channel
takes approximately 10
μ
s.
Write “1” to the HEN (Handset Enable) bit in the Codec
Configuration register to power-up the handset codec chan-
nel (ADC and DAC). Power up of the handset codec chan-
nel takes approximately 10
μ
s.
Write “1” to the MSEN (Monitor Speaker Enable) bit in the
Codec Configuration register to power up the monitor
speaker DAC. Power-up of the monitor speaker DAC takes
approximately 10
μ
s.
BOOT-UP SEQUENCE
The AD1801 boot process is a combination of software and
hardware operations. Because much of the boot process is
driven by software, it can be performed in a number of ways.
The following steps provide a rough guideline.
1. Once the power supplies have stabilized, the RESET inter-
rupt vectors the DSP program counter to DSP program
memory address 0x2000, which is the first ROM address
when PMOVLAY = 4, and is the default after DSP reset. It
then starts to execute the instructions which the OEM has
programmed into on-chip ROM. These instructions would
typically include DSP I/O writes to configure DSP resources
(such as the SPORTS) and the IDMA registers (such as the
DAGs).
Table XIII. Power State Transitions
Time Required
for Transition
Indicator to DSP of
Transition Completion
Initial State
Final State
Transition Trigger (Bits in CC Register)
2
1[M, H, S]
2C
1[M, H, S]
1
1S
1
1H
1
1M
2
1
2C
1
2
2C
2[C]**
3[C]**
2[C]**
4[C]**
2[C]**
5[C]**
1[M, H, S]
2
1[M, H, S]
2C
1S
1
1H
1
1M
1
1
2
1
2C
2C
2
3[C]**
2[C]**
4[C]**
2[C]**
5[C]**
2[C]**
CEN Set to 1, [MEN, HEN, MSEN] Set to 1
CEN Reset to 0, SBEN Set to 1
CEN Set to 1, [MEN, HEN, MSEN] Set to 1
CEN Reset to 0, SBEN Reset to 0
MSEN Set to 1
MSEN Reset to 0
HEN Set to 1
HEN Reset to 0
MEN Set to 1
MEN Reset to 0
CEN Set to 1, SBEN Don’t Care
CEN Reset to 0, SBEN Reset to 0
CEN Set to 1, SBEN Don’t Care
CEN Reset to 0, SBEN Set to 1
CEN Reset to 0, SBEN Reset to 0
CEN Reset to 0, SBEN Set to 1
DSP Executes IDLE Instruction
DSP Stops Executing IDLE
See Power State 4 Paragraph
See Power State 4 Paragraph
See Power State 5 Paragraph
See Power State 5 Paragraph
< 700 ms*
< 100
μ
s*
< 100
μ
s*
< 100
μ
s*
< 100
μ
s
< 100
μ
s
< 100
μ
s
< 100
μ
s
< 100
μ
s
< 100
μ
s
< 700 ms*
< 150 ns*
< 30 ns*
< 120 ns*
< 700 ms*
< 30 ns*
None
None
See PS4 Par.
< 7
μ
s
See PS5 Par.
> 280
μ
s
CEN Read Back as 1
CEN Read Back as 0
CEN Read Back as 1
CEN Read Back as 0
None
None
DSP SPORT Activity
SPORT Activity Stops
DSP SPORT Activity
SPORT Activity Stops
CEN Read Back as 1
CEN Read Back as 0
CEN Read Back as 1
CEN Read Back as 0
None
None
None
None
PWDACK Pin HI
PWDACK Pin LO
PWDACK Pin HI
PWDACK Pin LO
*
*Delay will be increased by 140 ms if the AD1801 has not yet autocalibrated itself. Autocalibration is executed the first time the AD1801 transitions to Power State
1 after a hard reset, i.e., a reset initiated by either the RESET pin or
RESET
pin. If the transition to Power State 1 is aborted before it is completed (by resetting
CEN to 0), autocalibration is postponed until the next transition to Power State 1. However, once autocalibration is actually begun, which occurs at the end of the
nominal transition to Power State 1, it cannot be interrupted and attempts to abort the transition will be ignored until autocalibration has been completed.
**Power States 3, 4 and 5 can be entered only from Power State 2. Power States 3C, 4C and 5C can be entered only from Power State 2C.
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PDF描述 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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