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參數(shù)資料
| 型號(hào)： | AD1801 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Single-Chip Fax/Data/ Voice Modem(單片的傳真/數(shù)據(jù)/語音調(diào)制解調(diào)器) |
| 中文描述： | 單芯片傳真/數(shù)據(jù)/語音調(diào)制解調(diào)器（單片的傳真/數(shù)據(jù)/語音調(diào)制解調(diào)器） |
| 文件頁數(shù)： | 44/52頁 |
| 文件大?。?/td> | 348K |
| 代理商： | AD1801 |
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AD1801
–44–
REV. 0
2. Beginning at 0x002C, any number of housekeeping instruc-
tions can be executed prior to the DSP entering actual power-
down. These instructions must ensure that the codec is
powered down before continuing with this procedure. See
the CEN (Codec Enable) bit located in the DSP I/O mapped
register CC (Codec Configuration) for detailed information
on how to power-down the codec and check its power-up/
-down status. These instructions must also program the
“SPORT1 Autobuffer/Power-Down Control Register”
memory mapped at location 0x3FEF to 0x0XXX unless these
settings are made in advance. This sets:
XTALDIS
= 0, which causes the crystal oscillator
to stay enabled during DSP power-
down.
XTALDELAY = 0, which causes the DSP startup delay
to be less than 100 cycles.
PDFORCE
= 0, which should never be set to “1” in
the AD1801.
PUCR
= 0, which avoids a DSP power-up reset
so instruction execution continues
in the power-down handler after
power-up.
3. The DSP must write a “1” to the SBWAIT (System Bus
Wait) bit in DSP I/O mapped register DC. Any bus transac-
tions to the AD1801 started AFTER this point will be ex-
tended (through the assertion of the IOCHRDY/
WAIT
pin)
until the DSP wakes up again after being powered down by
the steps below. Any currently active bus access to the
AD1801 will be completed without bus cycle extension to
insure that the AD1801 doesn’t assert IOCHRDY/
WAIT
too
close to the end of a bus access.
4. The DSP must poll the PD bit in the DSP I/O mapped DC
register until it is read as a “1.” In most systems, this will
require no more than 1
μ
s. When read as a “1,” this indicates
that there is either no active system bus access to the
AD1801, or that a bus access to the AD1801 has been
stalled through the assertion of the IOCHRDY/
WAIT
pin.
Once read as a “1,” it is safe to power down the DSP and
stop the AD1801 internal clocks.
5. The DSP powers itself down with the execution of an IDLE
instruction. This completes the transition into Power State 4.
While the AD1801 is now mostly powered down, it contin-
ues decoding bus traffic waiting for any AD1801 access, read
or write, which will initiate AD1801 wakeup. Note that ac-
cesses to PCMCIA external devices will occur without wak-
ing up the AD1801.
The process of entering Power State 4 may be aborted up
until step 4 where SBWAIT is set to “1.” Once set to “1,”
Steps 4 and 5 must also be executed for proper future
AD1801 operation. If SBWAIT was not set to “1,” Power
State 4 can be aborted by first resetting SBWAIT to a “0,”
that signals an early exit to the AD1801, and then executing an
RTI instruction which will exit the power-down handler.
“System Control” register at 0x3FFF. Finally, note that the
PMODE, PSPORT and SPCHAN bits in the DSP I/O mapped
register DC, which specify DSP serial port usage, must also be
defined before enabling related codec channels.
If the CEN (Codec Enable) bit is reset to “0” (see DSP I/O
mapped register CC), the process of entering Power State 2 will
be initiated. The DSP may poll the codec (by reading the CEN
bit and waiting for an echo of “0”) to determine when Power
State 2 is actually entered.
Power State 3
DSP:
Idle
Codec:
Powered Down or in Standby
Interface:
Responsive
Crystal:
Enabled
Power State 3 will be entered if an IDLE instruction is executed
by the DSP, provided the DSP is not currently servicing a
power-down interrupt. Note that the IDLE(n) DSP instruction
must not be used since the internal clock slow down caused by
this instruction will interfere with the AD1801 bus interface
logic.
In this Power State, the DSP is idle and the codec is powered
down.
When an unmasked interrupt occurs, the AD1801 will return to
Power State 2 immediately and service the interrupt.
Power State 4
DSP:
Powered Down
Codec:
Powered Down or in Standby
Interface:
Slow responsive
Crystal:
Enabled
Entering and exiting this Power State requires DSP code sup-
port. This code is outlined below. While in this Power State, the
AD1801 will not be immediately responsive to system bus ac-
cesses, but will extend bus cycles through the assertion of the
IOCHRDY/
WAIT
pin until able to respond. Any system bus
access to the AD1801, read or write, will wake the AD1801
from this Power State and return it to Power State 2 where the
AD1801 can respond to bus cycles. The system bus will be
stalled for no more than 7
μ
s, which is acceptable for both ISA
and PCMCIA buses. The ISA bus specifies a maximum stall of
15.6
μ
s, and the PCMCIA bus specifies a maximum stall of 12
μ
s.
Entering Power State 4:
1. The transition to Power State 4 is initiated by the assertion of
a nonmaskable power-down interrupt. The source of this
power-down interrupt may be: 1) the PC writing to the PD
bit in the PC I/O memory mapped register PCC; 2) the DSP
writing the PD bit in DSP I/O memory mapped register DC.
This interrupt will cause the DSP to vector to address
0x002C. The transition to this Power State may be indirectly
initiated by asserting the PWD (power-down pin) or the
PCMCIA power-down bit (bit PWRDN of register CSR0).
Either of these actions will cause an IRQL0 interrupt to the
DSP, causing it to vector to address 0x000C. In this inter-
rupt handler, the DSP may in turn write the PD bit. Note
that the DSP has access to two flag bits (PDRN and PDRM
in DSP I/O mapped register DC) that indicate the source of
an IRQL0 interrupt.
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| AD1803 | ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86% |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AD1803-0.4 | 制造商:Analog Devices 功能描述: |
| AD1803JRU | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
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