參數(shù)資料
型號: AD1801
廠商: Analog Devices, Inc.
英文描述: Single-Chip Fax/Data/ Voice Modem(單片的傳真/數(shù)據(jù)/語音調(diào)制解調(diào)器)
中文描述: 單芯片傳真/數(shù)據(jù)/語音調(diào)制解調(diào)器(單片的傳真/數(shù)據(jù)/語音調(diào)制解調(diào)器)
文件頁數(shù): 24/52頁
文件大?。?/td> 348K
代理商: AD1801
AD1801
–24–
REV. 0
Table IV. Interrupt Architecture (Continued)
DSP Accessible Signals
Description
PCIRQ
DSPIX
DSP writable bit to request an interrupt on the system bus.
DSP writable bit to acknowledge/clear the DSP interrupt. Interrupt is acknowledged/cleared when
DSPIX is set to “1.” Writing this bit has no effect when in PCMCIA mode with IntrACK0 = 1.
DSP writable bit to acknowledge/clear the RING interrupt. Writing this bit has no effect when in
PCMCIA mode with IntrACK0 = 1.
RNGIX
Host Accessible Signal
(Not Including Those in
PCMCIA/PnP Registers)
Description
DSPIE
RNGIE
DSPI
RNGI
DSPIA
Host writable bit which enables DSP interrupts.
Host writable bit which enables RING interrupts.
Host readable bit which indicates whether an interrupt is pending from the DSP.
Host readable bit which indicates whether an interrupt is pending from the RING pin.
Host writable bit to acknowledge/clear the DSP interrupt. Writing this bit has no effect when in
PCMCIA mode with IntrACK0 =1.
Host writable bit to acknowledge/clear the RING interrupt. Writing this bit has no effect when in
PCMCIA mode with IntrACK0 =1.
RNGIA
Table V. DSP Interrupt Mapping
I
nterrupt Source
Interrupt Vector Address
Comment
RESET
Power Down
Host PC (IRQ2)
IO0 Pin (IRQL1)
PCMCIA Power-Down (IRQL0)
SPORT 0 Transmit
SPORT 0 Receive
RING Pin (IRQE)
SPORT 1 Transmit
SPORT 1 Receive
Timer
0x2000 (ROM)
0x002C (RAM)
0x0004 (RAM)
0x0008 (RAM)
0x000C (RAM)
0x0010 (RAM)
0x0014 (RAM)
0x0018 (RAM)
0x0020 (RAM)
0x0024 (RAM)
0x0028 (RAM)
Highest Priority
Triggered by Writing “1” to PD Bit in PCC Register
Triggered by Rising or Falling Edge of IO0 Pin
Triggered While PWRDN = 1 in CSR0 or
PDW
Pin LO
Triggered by Falling Edge on RING Pin
Lowest Priority
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