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參數(shù)資料
| 型號(hào)： | AD1801 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Single-Chip Fax/Data/ Voice Modem(單片的傳真/數(shù)據(jù)/語音調(diào)制解調(diào)器) |
| 中文描述： | 單芯片傳真/數(shù)據(jù)/語音調(diào)制解調(diào)器（單片的傳真/數(shù)據(jù)/語音調(diào)制解調(diào)器） |
| 文件頁數(shù)： | 25/52頁 |
| 文件大?。?/td> | 348K |
| 代理商： | AD1801 |
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AD1801
–25–
REV. 0
DMA Controller
The AD1801’s DMA Controller block ensures that both pro-
gram code and data supplied by the host PC is loaded into on-
chip memory in an efficient manner. The address counter in
the IDMA Port can facilitate block transfers using the auto
incrementing mechanism.
The host PC uses two locations in its I/O memory map for
transferring data to and from on-chip program/data memory.
One location allows the host PC effective access to the IDMA
Control (IDMAC) register. This register is used by the host PC
to program the 14-bit memory address counter (register bits
13:0) and 1-bit destination indicator (Register Bit 14). This
register needs only to be programmed once for block transfers
to/from the same type of memory, since the address counter is
automatically incremented for each IDMA read/write operation.
The destination indicator is programmed to a 1 whenever the
host PC wishes to access data memory, otherwise program
memory will be accessed. The second I/O location is reserved
for the 16-bit data word provided to or supplied by the host PC.
This location is mapped to a read-only Memory Data Input (MDI)
register and to a write-only Memory Data Output (MDO) register.
When accessing the 24-bit program memory, two host PC read
or write cycles from MDI or to MDO, respectively, are re-
quired. The first program memory access, or any odd num-
bered access following an IDMAC register update applies to the
Most Significant (MS) 16 bits of the 24-bit program data word
(Bits 23:8). The second access, or any even numbered access
following an IDMAC register update applies to the Least Sig-
nificant (LS) eight bits of the 24-bit program word (Bits 7:0).
Bits MDO(15:8) are ignored by the AD1801 in this case for
write operations; the host PC will receive valid data on
MDI(7:0) for read operations. The IDMA address counter is
not incremented until after the LS byte portion of the 24-bit
program data word has been addressed. If the IDMAC register
is updated before the second half of a program data read/write
operation is executed, the capability to access the LS byte for
the previous address value will be lost; the DMA controller will
access the MS 16 bits of the data at the new address during the
following program memory read/write operations.
When accessing data memory, only a single read or write cycle is
required since the 16-bit memory words are accommodated by
the DMA bus, IAD(15:0), and the host PC data bus, SD(15:0);
however, the IDMAC register must be programmed first to let
the DMA controller know that the next host PC initiated
memory access cycles are targeted for data memory and to de-
fine a starting address. The IDMAC register is incremented
upon completion of each successive write/read operation to/from
the memory data registers, MDO and MDI.
The DMA Controller is able to provide the host PC with data
without use of wait states for back-to-back read and write opera-
tions. The DSP continues to run at full speed while synchroni-
zation is achieved over a DMA bus cycle request; only then is a
single DMA cycle stolen from the DSP. The entire DMA bus
!FUNC0EN
RST
SET
CLR
STICKY
LATCH
Q
DSPIE
PCIRQ
DSPIX
DSPIA
INTR0 (WR=0)
(PCMCIA * INTRACK0)
DSPI
RNGIE
RING PIN
RNGIX
RNGIA
INTR0 (WR=0)
(PCMCIA * INTRACK0)
RNGI
!FUNC1EN
!PCMCIA+!INTRACK1
INT1 PIN
INTR1 (WR=0)
(PCMCIA * INTRACK1)
!FUNC2EN
!PCMCIA+!INTRACK2
INT2 PIN
INTR2 (WR=0)
(PCMCIA * INTRACK2)
INTR0
INTR1
INTR2
IREQ1EN
IREQ2EN
IRQ3 (ISA)
IRQ4 (ISA)
IRQ5 (ISA)
IRQ7(ISA)
IRQ9 (ISA)
IRQ10 (ISA)
IRQ11(ISA)
IRQ12 (ISA)
IRQ15 (ISA)
IRQSEL3
IRQSEL4
IRQSEL5
IRQSEL7
IRQSEL9
IRQSEL10
IRQSEL11
IRQSEL12
IRQSEL15
IREQ
(PCMCIA)
500ns
DELAY ARBITER
0
1
0
1
!FUNC0EN
RST
SET
CLR
STICKY
LATCH
Q
RST
SET
CLR
STICKY
LATCH
Q
0
1
RST
SET
CLR
STICKY
LATCH
Q
0
1
PCMCIA
0
1
IREQ0EN
PNPIRQnEN
Figure 12. Interrupt Structure
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