參數(shù)資料
型號(hào)： AD1801
廠商： Analog Devices, Inc.
英文描述： Single-Chip Fax/Data/ Voice Modem(單片的傳真/數(shù)據(jù)/語(yǔ)音調(diào)制解調(diào)器)
中文描述： 單芯片傳真/數(shù)據(jù)/語(yǔ)音調(diào)制解調(diào)器（單片的傳真/數(shù)據(jù)/語(yǔ)音調(diào)制解調(diào)器）
文件頁(yè)數(shù)： 23/52頁(yè)
文件大小： 348K
代理商： AD1801
AD1801
–23–
REV. 0
Interrupt Architecture
The signals used in generating interrupts are shown in Table IV.
Table IV. Interrupt Architecture
Pins
Description
PCM_
ISA
RING
INT1
Indicates that the AD1801 is in PCMCIA mode or ISA mode.
Falling edge signal indicates a ring interrupt.
External Function 1 interrupt request pin. Assumed to be a level signal if IntrACK1 = 0. Can be edge if
IntrACK1 = 1.
External Function 2 interrupt request pin. Assumed to be a level signal if IntrACK2 = 0. Can be edge if
IntrACK2 = 1.
INT2
PCMCIA/
PnP Signals
Description
Func0En
In PCMCIA mode, the Func0En bit is the “Enable Function” bit in the Configuration Option Register,
COR0[0]. In PnP mode, the Func0En bit is the “active” bit for logical device zero.
In PCMCIA mode, the Func1En bit is the “Enable Function” bit in the Configuration Option Register,
COR1[0]. In PnP mode, the Func1En bit is deasserted.
In PCMCIA mode, the Func2En bit is the “Enable Function” bit in the Configuration Option Register,
COR2[0]. In PnP mode, the Func2En bit is deasserted.
PCMCIA defined bit that determines the mode for clearing interrupts. When IntrACKx = 0, interrupts are
cleared at the function (i.e., by the DSP or Host writing to ACK bits). When IntrACKx = 1, interrupts are
cleared via the Intr bit (CSRx[1]). IntrACKx is CSRx[0]. The assertion of any of the three IntrACKs (from the
three CSR registers) will cause the entire part to behave as if all three IntrACKs were asserted. Reads of the
IntrACK bits will always return what was written.
CSR0[1]. Reads of Intr0 indicate if the DSP/RING interrupt is asserted even if the interrupt pin enable 0
(IREQ0En) is deasserted.
CSR1[1]. Reads of Intr1 indicate if the external Function 1 interrupt is asserted even if the interrupt pin enable 1
(IREQ1En) is deasserted.
CSR2[1]. Reads of Intr2 indicate if the external Function 2 interrupt is asserted even if the interrupt pin enable 2
(IREQ2En) is deasserted.
A write of “0” to the Intr0 bit, CSR0[1]. When IntrACK0 = 1, this causes both the DSP and RING interrupts to
clear. When IntrACKx = 0, the write has no effect.
A write of “0” to the Intr1 bit, CSR1[1]. When IntrACK1 = 1, this causes the External Function 1 (INT1) inter-
rupt to clear. When IntrACK1 = 0, the write has no effect.
A write of “0” to the Intr2 bit, CSR2[1]. When IntrACK2 = 1, this causes the External Function 2 (INT2) inter-
rupt to clear. When IntrACK2 = 0, the write has no effect.
Host writable bit (in the PCMCIA control registers) that enables DSP/RING interrupts on the IREQ# pin.
PCMCIA mode only. (Created from COR0[2].)
Host writable bit (in the PCMCIA control registers) that enables External Function 1 interrupts on the IREQ#
pin. PCMCIA mode only. (Created from COR1[2].)
Host writable bit (in the PCMCIA control registers) that enables External Function 2 interrupts on the IREQ#
pin. PCMCIA mode only. (Created from COR2[2].)
Nine versions of this signal exists for each of the nine ISA interrupt levels possible; assertion is mutually exclusive.
IRQSELn signals are created from the PnP IRQ level register.
Func1En
Func2En
IntrACKx
Intr0
Intr1
Intr2
Intr0 (WR = 0)
Intr1 (WR = 0)
Intr2 (WR = 0)
IREQ0En
IREQ1En
IREQ2En
IRQSELn
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