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參數(shù)資料
| 型號： | AD1801 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Single-Chip Fax/Data/ Voice Modem(單片的傳真/數(shù)據(jù)/語音調(diào)制解調(diào)器) |
| 中文描述： | 單芯片傳真/數(shù)據(jù)/語音調(diào)制解調(diào)器（單片的傳真/數(shù)據(jù)/語音調(diào)制解調(diào)器） |
| 文件頁數(shù)： | 45/52頁 |
| 文件大小： | 348K |
| 代理商： | AD1801 |
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AD1801
–45–
REV. 0
Exiting Power State 4:
6. There are two conditions under which the DSP will be pow-
ered up, and Power State 4 exited. The first is the host PC
initiating a read or write access to the AD1801. The second
is a logic transition (either LO to HI or HI to LO) on any of
the following input signals: RING, INT1, and INT2.
7. When the host initiates the read or write access, the AD1801
asserts the IOCHRDY/
WAIT
pin to extend the bus cycle
until it can respond, and begins the process of powering up
the DSP. When the wake is caused by a transition on RING,
INT1, or INT2, the IOCHRDY/
WAIT
signal is not asserted.
Powering up the DSP requires about 6
μ
s.
8. When the DSP wakes up, it continues executing code where
it left off in the power-down handler. The first instruction
should reset the SBWAIT bit to “0” to allow the completion
of the extended bus cycle.
9. Any number of housekeeping instructions can now be ex-
ecuted before the power-down interrupt handler is exited by
an RTI instruction.
Power State 4 may also be exited with the assertion of a pin
reset, RESET or
RESET
.
Power State 5
DSP:
Powered Down
Codec:
Powered Down or in Standby
Interface:
Nonresponsive
Crystal:
Disabled
WARNING: When in this Power State, bus accesses to the
AD1801 are not possible. This Power State must not be used if
ISA PnP or PCMCIA configuration register access must be
maintained.
Entering and exiting this Power State requires DSP code
support. This code is outlined below. While in this Power
State, the AD1801 will not be responsive to system bus ac-
cesses. Any system bus access to the AD1801, read or write,
will, however, wake the AD1801 from this Power State into
Power State 2. On the order of 280
μ
s plus a crystal settle
time will be necessary to wake the AD1801. Unlike waking
from Power State 4, bus cycles will not be extended when
waking from this Power State.
Entering Power State 5:
1. The transition to Power State 5 is initiated by the assertion of
a nonmaskable power-down interrupt. The source of this
power-down interrupt may be: 1) the PC writing to the PD
bit in the PC I/O memory mapped register PCC; 2) the DSP
writing the PD bit in DSP I/O memory mapped register DC.
This interrupt will cause the DSP to vector to address
0x002C. The transition to this Power State may be indirectly
initiated by asserting the PWD (power-down pin) or the
PCMCIA power-down bit (bit PWRDN of register CSR0).
Either of these actions will cause an IRQL0 interrupt to the
DSP, causing it to vector to address 0x000C. In this inter-
rupt handler, the DSP may in turn write the PD bit. Note
that the DSP has access to two flag bits (PDRN and PDRM
in DSP I/O mapped register DC), which indicate the source
of an IRQL0 interrupt.
2. Beginning at 0x002C, any number of housekeeping instruc-
tions can be executed prior to the DSP entering actual power-
down. These instructions must insure that the codec is
powered down before continuing with this procedure. See
the CEN (Codec Enable) bit located in the DSP I/O mapped
register CC (Codec Configuration) for detailed information
on how to power down the codec and check its power up/
down status. These instructions must also program the
“SPORT1 Autobuffer/Power-Down Control Register”
memory mapped at location 0x3FEF to 0x0XXX unless
these settings are made in advance. This sets:
XTALDIS
= 1, which causes the crystal oscillator to
power down during DSP power-down.
XTALDELAY
= 1, which causes the DSP startup delay
to be 4096 clock cycles.
PDFORCE
= 0, which should never be set to “1” in
AD1801.
PUCR
= 0, which avoids a DSP power up reset
so instruction execution continues
in the power-down handler after
power-up.
3. The DSP powers itself down with the execution of an IDLE
instruction. This completes the transition into Power State 5.
While the AD1801 is now mostly powered down, it contin-
ues decoding bus traffic waiting for any AD1801 access, read
or write, that will initiate AD1801 wakeup. Note that ac-
cesses to PCMCIA external devices will occur without wak-
ing up the AD1801.
The process of entering Power State 5 may be aborted up
until Step 3 where the IDLE instruction is executed. Power
State 5 can be aborted by first resetting SBWAIT to a “0,”
which signals an early exit to the AD1801, and then execut-
ing an RTI instruction which will exit the power-down handler.
Exiting Power State 5:
4. There are two conditions under which the DSP will be pow-
ered up, and Power State 5 exited. The first is the host PC
initiating a dummy read access to the AD1801. This bus
access to the AD1801, and all others until the AD1801 is
awake, is lost. The second is a logic state transition (either
LO to HI or HI to LO) on any of the following input signals:
RING, INT1, and INT2.
5. When the DSP wakes up, it continues executing code where
it left off in the power-down handler. The first instruction
should reset the SBWAIT bit to “0” to clear the power-down
logic.
6. Any number of housekeeping instructions can now be ex-
ecuted before the power-down interrupt handler is exited by
an RTI instruction. It may be desirable to send an interrupt
to the host PC to signal AD1801 wakeup.
Power State 5 may also be exited with the assertion of a pin
reset, RESET or
RESET
.
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