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參數(shù)資料
| 型號(hào)： | AD1801 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Single-Chip Fax/Data/ Voice Modem(單片的傳真/數(shù)據(jù)/語(yǔ)音調(diào)制解調(diào)器) |
| 中文描述： | 單芯片傳真/數(shù)據(jù)/語(yǔ)音調(diào)制解調(diào)器（單片的傳真/數(shù)據(jù)/語(yǔ)音調(diào)制解調(diào)器） |
| 文件頁(yè)數(shù)： | 42/52頁(yè) |
| 文件大?。?/td> | 348K |
| 代理商： | AD1801 |
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AD1801
–42–
REV. 0
MADL[1:0]
Modem ADC Gain Level Select. Least significant bit represents +6.0 dB.
00 = 0.0 dB Gain (default)
01 = +6.0 dB Gain
10 = +12.0 dB Gain
11 = Reserved
Modem DAC Mute.
0 = Enabled
1 = Muted (default)
Modem DAC Attenuation Level Select. Least significant bit represents –1.0 dB.
00000 = 0 dB Attenuation (default)
11111 = –31 dB Attenuation
Monitor Speaker Attenuation Level.
00 = 0.0 dB Attenuation
01 = –6.0 dB Attenuation
10 = –12.0 dB Attenuation
11 = Muted (default)
Default state after system reset: 0000 0000 1000 0011 (0x0083).
Handset Levels
Mnemonic: HL
MDAM
MDAL[4:0]
SDAL[1:0]
Access: Read/Write
Address: 0x209
5
1
a
t
a
D
4
1
a
t
a
D
3
1
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D
2
1
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1
1
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D
0
1
a
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a
D
9
a
t
a
D
8
a
t
a
D
S
D
A
H
E
G
M
H
s
e
r
s
e
r
3
L
D
A
H
2
L
D
A
H
1
L
D
A
H
0
L
D
A
H
7
a
t
a
D
6
a
t
a
D
5
a
t
a
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4
a
t
a
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3
a
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2
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1
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t
a
D
0
a
t
a
D
M
S
A
D
H
M
L
A
D
H
s
e
r
4
L
A
D
H
3
L
A
D
H
2
L
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H
1
L
A
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H
0
L
A
D
H
HADS
Handset ADC Input Select.
0 = Mic (default)
1 = Line
Handset Mic Gain Enable.
0 = 0 dB Gain (default)
1 = +20 dB Gain
Handset ADC Gain Level Select. Least significant bit represents +1.5 dB.
0000 = 0.0 dB Gain (default)
1111 = +22.5 dB Gain
Handset DAC Speaker Mute.
0 = Enabled
1 = Muted (default)
Handset DAC Line Mute.
0 = Enabled
1 = Muted (default). Midscale voltage output on HSPKRP and HSPKRN
Handset DAC Attenuation Level Select. Least significant bit represents –1.5 dB.
00000 = +12.0 dB Gain
01000 = 0.0 dB Attenuation (default)
11111 = –34.5 dB Attenuation
Default state after system reset: 0000 0000 1100 1000 (0x00C8).
Modem Speaker Data
Mnemonic: MSD
HMGE
HADL[3:0]
HDALM
HDAL[4:0]
Access: Write
Address: 0x20A
5
1
a
t
a
D
4
1
a
t
a
D
3
1
a
t
a
D
2
1
a
t
a
D
1
1
a
t
a
D
0
1
a
t
a
D
9
a
t
a
D
8
a
t
a
D
5
1
D
S
M
4
1
D
S
M
3
1
D
S
M
2
1
D
S
M
1
1
D
S
M
0
1
D
S
M
9
D
S
M
8
D
S
M
7
a
t
a
D
6
a
t
a
D
5
a
t
a
D
4
a
t
a
D
3
a
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a
D
2
a
t
a
D
1
a
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a
D
0
a
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a
D
7
D
S
M
6
D
S
M
5
D
S
M
4
D
S
M
3
D
S
M
2
D
S
M
1
D
S
M
0
D
S
M
MSD[15:0]
Monitor Speaker Data. Writes to this register fill a 16 deep FIFO. If this FIFO underruns, the last sample will be
repeated to the monitor speaker DAC for up to 16 consecutive underruns; thereafter, midscale sample data is used for
all additional underruns. This avoids clicks due to momentary FIFO underruns (easing playback startup) and avoids
sustained dc output levels. Data written to this FIFO that would cause FIFO overrun is ignored. No status bits are
needed for this FIFO since it is locked to either the modem or handset sample rate (see the MSSR bit in register CC).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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