參數(shù)資料
型號(hào)： AD1801
廠商： Analog Devices, Inc.
英文描述： Single-Chip Fax/Data/ Voice Modem(單片的傳真/數(shù)據(jù)/語(yǔ)音調(diào)制解調(diào)器)
中文描述： 單芯片傳真/數(shù)據(jù)/語(yǔ)音調(diào)制解調(diào)器（單片的傳真/數(shù)據(jù)/語(yǔ)音調(diào)制解調(diào)器）
文件頁(yè)數(shù)： 17/52頁(yè)
文件大?。?/td> 348K
代理商： AD1801
AD1801
–17–
REV. 0
Plug And Play Card Configuration Controller
The AD1801 Plug And Play (PnP) module provides nine out-
put enables to the interrupt request pins, only one of which is
active after a PnP configuration session. The PnP module also
determines the card’s 7-bit I/O memory base address and pro-
vides an internal “card select” signal whenever the host PC
accesses an AD1801 programmable register or the general pur-
pose I/O port. The PNP_
STD
control input can be left uncon-
nected or tied HI to enable this function.
The single function PnP module in the AD1801 meets
Microsoft’s PC 97 requirements. This means that it provides
a minimum of seven I/O base locations and 7 interrupts as well
as performing a full 16-bit I/O address decode. Since in PCM-
CIA mode only a single interrupt request is required, all but one
of the ISA interrupt request pins are redefined when the
AD1801 is configured for PCMCIA mode. These dual function
pins are listed in Table I below. Since PCMCIA pin require-
ments exceed the minimum ISA requirements, two additional
ISA interrupt requests can be readily accommodated as is re-
flected in the table.
In addition, the AD1801 provides the core DSP with the means
to take the PnP function “off line” and permit the DSP access
to the PnP internal registers. This allows the DSP the option of
configuring the card at power-up, effectively bypassing the PnP
card configuration sequence.
Table I. ISA IRQ to PCMCIA Signal Mapping
AD1801
Pin Name
ISA Bus
Signal
PCMCIA Bus
Signal
External Function
Port-1 Signal
IRQ9/
IREQ
IRQ3
IRQ4/
INPK
IRQ5/
CHG
IRQ7/
SPKR
IRQ10/
CS
1
IRQ11/
RS
1
IRQ12/PD1
IRQ15
IRQ9
IRQ3
IRQ4
IRQ5
IRQ7
IRQ10
IRQ11
IRQ12
IRQ15
IREQ
INPACK
STSCHG
SPKR
CS
1
RS
1
PD1
The AD1801’s PnP data address is maintained in the Timing &
Control block, and the DMA Controller can be used to access
the PnP data from the DSP’s data memory without interrupting
the DSP, thus stealing no more than a single DSP cycle per
transfer. This is desirable since a PnP data request can occur at
any time during normal operations.
ISA Standard Mode Compatibility
The PnP or Standard mode select input, PNP_
STD
, is used to
enable/disable the PnP logic module. It can be tied to DV
DD
or
left unconnected to enable the PnP logic or tied to DGND if
PnP is not to be supported. An internal pull-up ensures that a
HI state is seen when the pin is left unconnected. This input is
available for the DSP to read. This allows the implementation
of schemes that require the DSP to determine a suitable PC I/O
space base address and PC interrupt for the I/O slave card when
the standard mode is active. The DSP must program a 13-bit
Default Base Address register with a 13-bit I/O Memory Base
address and a 4-bit Default Interrupt Select register for selecting
the active IRQ output. These registers are located in the
AD1801’s Timing & Control block and are active whenever
inputs PNP_
STD
and PCM_
ISA
are tied to DGND.
ADSP-2181 (DSP) INTERFACE
External Bus
The Windows modem function block interfaces to the ADSP-
2181’s external bus as an I/O peripheral to give the DSP access
to control registers, status bits and the I/O ports. Note that the
physical connections for this interface are made completely inside
the AD1801. A 7-bit base address A[10:4], starting at address
0x000 (see Table VII), plus a 4-bit destination address, A[3:0],
is decoded inside the Windows modem function. An I/O opera-
tion is qualified by an active
IOMS
signal initiated by the DSP.
Up to 16 bits of the DSP external data bus, D[15:0], are used
for passing data into and out of the Windows modem block; the
direction is determined by DSP memory and enables controls
RD
and
WE
. No wait states are required for internal DSP I/O
operations.
Internal DMA Port
The Windows modem function block interfaces to the ADSP-
2181’s internal DMA port to provide the host PC with the
means to access on-chip program and data memory. This com-
munications path is crucial to the operation of the AD1801; it
handles back-to-back host PC read or write operations for the
active bus interface, i.e., it sustains data transfers of 4.17
Mbytes/s over the ISA 16-bit data bus and 8 Mbytes/s over the
PC Card 16-bit data bus. This interface consists of a 16-bit
multiplexed address/data bus (IAD[15:0]), port read (
IRD
),
write (
IWR
), address latch (IAL) and start (
IS
) control pins
plus an acknowledge (
IACK
) output.
Timing and Control
The Windows modem block of the AD1801 uses the maximum
33.8688 MHz clock output generated by the DSP core from an
external 16.9344 MHz source. An external power-on reset
circuit or the host PC Bus reset provides a reset to both the core
DSP and Windows modem blocks; this forces the DSP to re-
boot from the internal ROM, rebuild the CIS table in the small
internal RAM, and initialize various Windows modem program-
mable registers. The RING input is used as one interrupt to
the DSP; a second interrupt is generated in the Windows mo-
dem Timing and Control block under host PC program control.
The DSP can selectively enable/disable the ring detection inter-
rupt via a bit in the DSP Control Register.
ISA Platform Compatible Host PC
The AD1801 is targeted for use in ISA add-on I/O slave card
designs. It provides a glueless interface to the ISA bus when-
ever the PCM_
ISA
control input is tied LO. All bus drivers are
compliant with ISA interface, electrical switching and drive
capability specifications. In particular, “fast” outputs are not
used as collectively they can induce glitches onto other bus
controls when they are simultaneously switched.
ISA 16-Bit Data Bus Interface
The AD1801’s ISA bus interface meets the timing specifica-
tions defined for 16-bit data ISA I/O standard access cycles.
This interface consists of a 16-bit address bus (SA[15:0]),
16-bit data bus (SD[15:0]), I/O read and write strobes (
IOR
and
IOW
), hardware reset RESET, IOCHRDY/
WAIT
,
IOCS16
/
IOIS16
, and nine interrupt requests. One of the
interrupts is selected for use by the card when it is configured;
the others remain in a high impedance state to allow other cards
their use. One bit in the AD1801’s DSP Control register serves
as the interrupt request to the PC. Its logic state is totally under
DSP program control. A bit in the PC Control register allows
the host PC to disable interrupt requests.
相關(guān)PDF資料
PDF描述
AD1803JRU U.S./International Modem DAA Line Codec Chipset
AD1803 ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86%
AD1804 U.S./International Modem DAA Line Codec Chipset
AD1804JRU ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86%
AD1812JST Silver Mica Capacitor; Capacitance:12pF; Capacitance Tolerance: 5%; Series:CD17; Voltage Rating:500VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:5.9mm; Leaded Process Compatible:No RoHS Compliant: No
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD1801JS 制造商:Rochester Electronics LLC 功能描述:- Bulk
AD1801JST-REEL 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel
AD1803 制造商:AD 制造商全稱:Analog Devices 功能描述:U.S./International Modem DAA Line Codec Chipset
AD1803-0.4 制造商:Analog Devices 功能描述:
AD1803JRU 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*