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參數(shù)資料
| 型號： | AD1801 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Single-Chip Fax/Data/ Voice Modem(單片的傳真/數(shù)據(jù)/語音調(diào)制解調(diào)器) |
| 中文描述： | 單芯片傳真/數(shù)據(jù)/語音調(diào)制解調(diào)器（單片的傳真/數(shù)據(jù)/語音調(diào)制解調(diào)器） |
| 文件頁數(shù)： | 35/52頁 |
| 文件大?。?/td> | 348K |
| 代理商： | AD1801 |
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AD1801
–35–
REV. 0
DSP I/O Memory Map
The AD1801 uses the DSP’s
IOMS
control and a 10-bit address A(9:0) to qualify DSP accesses to the internal CIS RAM, registers
and I/O port pins addressed according to the table below. The host PC will not access the CIS RAM until it detects the deactivation
of the
IREQ
bus signal after a system reset. The DSP has control over the deactivation of this pin after a reset has occurred via the
RDY bit in the DSP Control register. Under normal operations, the DSP will initialize the CIS RAM, then set the RDY bit; it will
not access the CIS memory again until after the next reset. An additional qualifying control, the DC register OVRIDE bit, is used to
determine whether the DSP can access the PnP function registers listed in the table or not. (The DSP must set this bit to a logical
“1” to temporarily take the PnP function “off-line” from the host PC in order to initialize or configure the PnP function itself. The
DSP clears this bit to return the PnP function back “on-line” for host PC use.)
Note: I/O memory space must be set for at least one wait state for proper AD1801 functionality.
Table X. DSP I/O Memory Map
DSP Address
Bits A[13:0]
Resource Accessed
Reads
Writes
Function
0x000–0x1FF
0x200
0x201
0x202
0x203
0x204
0x205
0x206
0x207
0x208
0x209
0x20A
reserved
DC
reserved
IP
reserved
reserved
CC
MSR
HSR
ML
HL
reserved
CIS RAM
DC
IPC
OP
BA
IS
CC
MSR
HSR
ML
HL
MSD
PCMCIA or PnP Attribute Configuration
DSP Control
I/O Port Control
I/O Port Data
Base Address
Interrupt Select
Codec Configuration
Modem Sample Rate
Handset Sample Rate
Modem Levels
Handset Levels
Monitor Speaker Data
Program Memory Organization
Program Memory Organization is controlled by the value of the PMOVLAY register. For the AD1801, valid settings of this register
are 0 and 4. When set to 0, all 16K of internal program memory RAM may be addressed. When set to 4, the upper 8K is swapped
out and replaced with the 4080 word ROM. After a DSP reset, PMOVLAY defaults to 4 and code execution commences at the first
ROM address, which is 0x2000.
Table XI. Program Memory Organization
PMOVLAY = 4 (Default after DSP Reset)
Program Memory
Address
0x0000–0x1FFF
0x2000–0x2FEF
0x2FF0–0x2FFF
0x3000–0x3FFF
Lower 8K of Internal RAM
4080 Words of Internal ROM
16 Words Reserved for Analog Devices
Reserved (Invalid Addresses)
PMOVLAY = 0
Address
Program Memory
0x0000–0x1FFF
0x2000–0x3FFF
Lower 8K of Internal RAM
Upper 8K of Internal RAM
CIS RAM
Access: Write Only
Address 0x000 to 0x1FF
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0
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6
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