參數(shù)資料
型號(hào)： AD1801
廠商： Analog Devices, Inc.
英文描述： Single-Chip Fax/Data/ Voice Modem(單片的傳真/數(shù)據(jù)/語(yǔ)音調(diào)制解調(diào)器)
中文描述： 單芯片傳真/數(shù)據(jù)/語(yǔ)音調(diào)制解調(diào)器（單片的傳真/數(shù)據(jù)/語(yǔ)音調(diào)制解調(diào)器）
文件頁(yè)數(shù)： 29/52頁(yè)
文件大?。?/td> 348K
代理商： AD1801
AD1801
–29–
REV. 0
ConfIndex[1]
Configuration Index bit 1 specifies the I/O addressing used. When set to “1,” I/O addresses specified by the base
and limit registers are passed to Function 2. When reset to “0,” all host I/O addresses are passed to Function 2.
This bit is valid only when ConfIndex[0] (Function Enable) is set to “1” (enabled).
Configuration Index bit 0 enables or disables Function 2. When set to “1,” Function 2 is enabled. When reset to
“0,” Function 2 is disabled and does not decode I/O addresses or generate
IREQ
.
PCMCIA Card Configuration and Status Registers
ConfIndex[0]
CSR0: PCMCIA Function 0 Configuration and Status Register
Access: Read/Write
Address: 0x402
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Chng
Status Change Detected. This bit indicates that one or more of the Pin Replacement register bits (CBVD1,
CBVD2, CRDY or CWProt) is set to one, normally causing the
CHG
signal (Pin 92) to be asserted; however, if
the SigChg bit (see below) is “1,” and the card is configured for an I/O interface, the
CHG
pin is asserted when
this bit is set.
Signal Change Enable/Disable. This bit is set and reset by the host to enable and disable a status change signal
from the status register. When this bit is set and the card is configured for the I/O interface, the Chng bit controls
Pin 92 (
CHG
). If no status change signal is desired, the bit should be set to zero and the
CHG
signal will be held
deasserted when the card is configured for I/O.
I/O Cycles Occur Only as 8-Bit Transfers. When the host can provide I/O cycles only using the SD7:SD0 data
path, the PCMCIA software will set this bit to a 1. The card is guaranteed that accesses to 16-bit registers will
occur as two byte accesses rather than a single 16-bit access. This information is useful when 16-bit and 8-bit
registers overlap.
On the AD1801, this bit is hardcoded to “0” (16-bit transfers allowed).
Reserved bits must be 0.
Audio Enable. This bit enables audio information to be sent to the Host Bus Adapter via the speaker pin
SPKR
(Pin 91) when configured for an I/O interface.
Power-Down. This bit is set to one to request that Function 0 enter a power-down state. PCMCIA software must
not place Function 0 into a power-down state while the Function’s READY pin in the LO (busy) state.
Interrupt Request Pending. This bit represents the internal state of the interrupt request. This value is available
whether or not interrupts have been configured. How the Intr bit is cleared is dependent up on how the IntrAck bit
is configured.
IntrAck = 0—Intr reflects the function’s interrupt request status. If the interrupt is cleared within the function, Intr
is reset by the function.
IntrAck = 1—Intr remains set even though the interrupt condition has been cleared (i.e., sticky). It is reset by
system software to indicate it is ready to receive another interrupt (implemented to support interrupt sharing).
Interrupt Acknowledge. This bit determines the response of the Intr bit. The functionality associated with the
IntrAck bit permits two or more functions to share the PC Card’s
IREQ
pin.
IntrAck = 0—When IntrAck is reset, Intr functions as described above to support a single interrupt
implementation.
IntrAck = 1—This causes the Intr bit to remain set even though the interrupt service routine has already serviced
the interrupt. Normally, the interrupt service routine clears the interrupt pending bit in a function specific register,
causing the Intr also to be cleared; however, to support interrupt sharing, the Intr bit is not cleared until PCMCIA
specific software is ready to handle the next interrupt request. When cleared by the PCMCIA software, other inter-
rupt requests that are pending can now be asserted over the PC Card’s
IREQ
pin.
CSR1: PCMCIA Function 1 Configuration and Status Register Access: Read/Write
SigChg
IOis8
Res
Audio
PwrDn
Intr
IntrAck
Address: 0x422
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Chng
Status Change Detected. This bit indicates that one or more of the Pin Replacement register bits (CBVD1,
CBVD2, CRDY or CWProt) is set to one, normally causing the
CHG
signal (Pin 92) to be asserted. However, if
the SigChg bit (see below) is “1,” and the card is configured for an I/O interface, the
CHG
pin is asserted when
this bit is set.
In the AD1801, Chng is “0” for Function 1.
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