參數(shù)資料
型號(hào)： AD1801
廠商： Analog Devices, Inc.
英文描述： Single-Chip Fax/Data/ Voice Modem(單片的傳真/數(shù)據(jù)/語音調(diào)制解調(diào)器)
中文描述： 單芯片傳真/數(shù)據(jù)/語音調(diào)制解調(diào)器（單片的傳真/數(shù)據(jù)/語音調(diào)制解調(diào)器）
文件頁數(shù)： 37/52頁
文件大?。?/td> 348K
代理商： AD1801
AD1801
–37–
REV. 0
PMODE
Port Mode Select. Selects which feature is supported by Pins 53 to 56, either the secondary PCMCIA function
port or a DSP serial port. When the DSP serial port is selected, data I/O to either the modem or the handset codec
channels is sacrificed since both serial ports are nominally used within the AD1801 for codec communication. See
the PSPORT and SPCHAN bits for further details on which codec channels are lost.
0 = PCMCIA Function Port 2 Activated (default)
1 = DSP Serial Port Activated (Modem or Handset DSP Data I/O is Sacrificed)
Port Serial Port Select. When PMODE is reset to “0,” this bit is ignored. When PMODE is set to “1,” this bit
selects which of the two DSP serial ports is connected to Pins 53 to 56. Note that this bit, together with the
SPCHAN bit, determine whether the modem or the handset codec channels are sacrificed when a DSP serial port
is assigned to Pins 53 to 56.
0 = DSP Port 0 Assigned to Pins 53 to 56 when PMODE = 1 (default)
1 = DSP Port 1 Assigned to Pins 53 to 56 when PMODE = 1
DSP Serial Port Channel Assignment. This bit selects which codec channel uses which DSP serial port for data
communication.
0 = Modem ADC and DAC Data Sent on SPORT 0, Handset ADC and DAC Data Sent on SPORT 1 (default)
1 = Modem ADC and DAC Data Sent on SPORT 1, Handset ADC and DAC Data Sent on SPORT 0
IO0 Pin Interrupt Acknowledge. Writing a “1” to this bit acknowledges and deasserts the DSP’s IRQL1 level interrupt. This
interrupt is asserted any time the logical input level on the IO0 pin changes state, either from HI to LO or LO to HI.
System Bus Wait. This bit is used by the DSP when servicing a power-down interrupt to support entering and
exiting AD1801 power-down mode. Once this bit is set to “1,” any future PC read/write cycles to the AD1801 will
be extended through the assertion of the IOCHRDY/
WAIT
pin. When reset to “0,” IOCHRDY/
WAIT
will be
deasserted (if asserted) to allow completion of an extended bus cycle. Resetting this bit to “0” is also the mecha-
nism of clearing a power-down interrupt initiated by the PC (see PD bit in the PC I/O mapped register PCC), so
this bit should be reset to “0” before exiting a power-down interrupt service routine, even if it was not set to “1.”
See the Power-Down section of this document for important additional details.
Power-Down Request from PCMCIA. This bit reflects the state of the PWRDN bit in the PCMCIA register
CSR0. While set to “1,” level interrupt IRQL0 is asserted to the DSP. This bit may be used by the DSP to deter-
mine the source of the IRQL0 interrupt, as the PDRN bit below also asserts IRQL0. Writing to this bit has no
effect. See the Power-Down section of this document for important additional details.
Power-Down Request from
PDN
pin. This bit reflects the state of the
PWD
pin. While the
PWD
pin is held
LO, level interrupt IRQL0 is asserted to the DSP. This bit may be used by the DSP to determine the source
of the IRQL0 interrupt, as the PDRM bit above also asserts IRQL0. Writing to this bit has no effect. See the
Power-Down section of this document for important additional details.
AD1801 Power-Down. Writing a “1” to this bit initiates the process of powering down the AD1801. Writing a “0” to
this bit has no effect. When read as a “1,” this bit indicates that there is no active nonextended system bus access to the
AD1801. See the Power-Down section of this document for further clarification and important additional details.
Default state after reset: 0000 0000 0000 0000 (0x0000).
I/O Port Control
Mnemonic: IPC
PSPORT
SPCHAN
IO0IA
SBWAIT
PDRM
PDRN
PD
Access: Read/Write
Address 0x201
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SDIE
Serial Memory Port Data Direction. Determines directionality of the SDATA pin.
0 = SDATA is an Output Pin with Logic Level Set by SDO Bit (see OP register).
1 = SDATA is an Input Pin (default).
Serial Data Enable Control Direction. Determines directionality of the SEN pin.
0 = SEN is an Output Pin with Logic Level Set by SEN Bit (see OP register) (default).
1 = SEN is an Input Pin.
Serial Data Clock Direction. Determines directionality of the SCK pin.
0 = SCK is an Output Pin with Logic Level Set by SCK Bit (see OP register) (default).
1 = SCK is an Input Pin.
I/O Port Control. Defines directionality of associated I/O port Pins IO7 through IO0.
0 = Output
1 = Input (default)
Default state after system reset: 0000 0001 1111 1111 (0x01FF).
SENIE
SCKIE
IPC[7:0]
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