參數(shù)資料
型號： AD1801
廠商： Analog Devices, Inc.
英文描述： Single-Chip Fax/Data/ Voice Modem(單片的傳真/數(shù)據(jù)/語音調(diào)制解調(diào)器)
中文描述： 單芯片傳真/數(shù)據(jù)/語音調(diào)制解調(diào)器（單片的傳真/數(shù)據(jù)/語音調(diào)制解調(diào)器）
文件頁數(shù)： 41/52頁
文件大小： 348K
代理商： AD1801
AD1801
–41–
REV. 0
SBEN
Codec Standby Enable. If either this bit or the CEN (Codec Enable) bit is set to “1,’’ the process of powering up the
AD1801’s codec voltage reference is initiated. If both this bit and the CEN bit are reset to “0,” the process of power-
ing down the AD1801’s codec voltage reference is initiated. Approximately 700 ms are required to power up the
codec voltage reference while only 30 ns are required to power it down. This bit may be used to keep the codec volt-
age reference powered up when the rest of the codec is powered down, which results in a much quicker power-up
sequence. See the CEN bit for further details.
0 = Codec Powered Down (Provided CEN = 0) (default)
1 = Codec in Standby (Provided CEN = 0)
Codec Enable. When a “1” is written to this bit, the process of powering up the AD1801 codecs is initiated. When a
“0” is written to this bit, the process of powering down the AD1801 codecs is initiated. When read as a “0,” the codecs
are either powered down or in the process of powering up. When read as a “1,” the codecs are either powered up or in
the process of powering down. Therefore, completion of the process of powering up or down can be detected by writ-
ing the appropriate value to this bit and reading this bit until the written value is echoed. Power-up normally requires
no more than 700 ms, but up to 840 ms will be required the first time the codecs are powered up after an AD1801
reset, since this is when the codecs perform an autocalibration. Note that if the codecs are first put in standby using
the SBEN bit (and given 700 ms time to complete the transition into standby), only 30 ns will be required after set-
ting the CEN bit to “1” to complete the power-up process. Powering down the codecs never requires more than
150 ns. See Table XII for a complete summary.
Default state after system reset: 0000 0000 0000 0000 (0x0000).
Modem Sample Rate
Mnemonic: MSR
CEN
Access: Read/Write
Address: 0x206
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MSR[15:0]
Modem Sample Rate. Together with MSM[15:0] (Modem Sample Rate Modifier) in the CC register, these bits
define the conversion rate for the modem ADC and DAC channels. If the MSSR bit (Monitor Speaker Sample Rate
Select) in register CC is reset to “0” (default), these bits also define the conversion rate for the monitor speaker DAC.
With a 16.9344 MHz clock input on the XTALI pin, one LSB represents: exactly 1 Hertz when MSM[1:0] = 00;
exactly 8/7 Hertz when MSM[1:0] = 01; and exactly 10/7 Hertz when MSM[1:0] = 10. Permitted settings of
MSR[15:0] range from: 5400 to 48000 when MSM[1:0] = 00; 4725 to 42000 when MSM[1:0] = 01; and 3780 to
33600 when MSM[1:0] = 10. Resultant sample rate, regardless of MSM[1:0] setting, always ranges from 5400 Hz
to 48000 Hz.
Default state after system reset: 0001 1100 0010 0000 (0x1C20) which is 7200 Hz with MSM[1:0] = 00.
Handset Sample Rate
Mnemonic: HSR
Access: Read/Write
Address: 0x207
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HSR[15:0]
Handset Sample Rate. Defines the conversion rate for the Handset ADC and DAC channels. If the MSSR (Monitor
Speaker Sample Rate select) bit in register CC is set to “1,” these bits also define the conversion rate for the monitor
speaker DAC. One LSB represents exactly 1 Hertz, assuming a 16.9344 MHz clock input on the XTALI pin. Usable
range is 5400 Hz (0x1518) to 48000 Hz (0xBB80).
Default state after system reset: 0001 1111 0100 0000 (0x1F40) which is 8 kHz.
Modem Levels
Mnemonic: ML
Access: Read/Write
Address: 0x208
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