參數(shù)資料
型號: 8XC196LX
英文描述: 8XC196Lx - 8XC196Lx Supplement to 8X196Kx. 8X196Jx. 87C196CA User's Manual
中文描述: 8XC196Lx - 8XC196Lx補編8X196Kx。 8X196Jx。 87C196CA用戶手冊
文件頁數(shù): 86/136頁
文件大?。?/td> 659K
代理商: 8XC196LX
8XC196LXSUPPLEMENT
8-20
J_DLY
Address:
Reset State:
1F58H
00H
The J1850 delay (J_DLY) register allows you compensate for the inherent propagation delays and to
accurately resolve bus contention during arbitration. This byte register can be directly addressed
through windowing
7
0
DLY4
DLY3
DLY2
DLY1
DLY0
Bit
Number
Bit
Mnemonic
Function
7:5
Reserved; for compatibility with future devices, write zeros to these bits.
4:0
DLY4:0
Delay Time
These five bits specify the desired propagation delay between the J1850
controller circuitry and the off-chip transceiver device, in units of
microseconds (μs).
Figure 8-18. J1850 Delay (J_DLY) Register
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