
iii
CONTENTS
CHAPTER 1
GUIDE TO THIS MANUAL
1.1
MANUAL CONTENTS................................................................................................... 1-1
1.2
RELATED DOCUMENTS.............................................................................................. 1-2
CHAPTER 2
ARCHITECTURAL OVERVIEW
2.1
MICROCONTROLLER FEATURES.............................................................................. 2-1
2.2
BLOCK DIAGRAM......................................................................................................... 2-2
2.3
INTERNAL TIMING........................................................................................................ 2-2
2.4
EXTERNAL TIMING ...................................................................................................... 2-5
2.5
INTERNAL PERIPHERALS........................................................................................... 2-6
2.5.1
I/O Ports ....................................................................................................................2-7
2.5.2
Synchronous Serial I/O Port .....................................................................................2-7
2.5.3
Event Processor Array ..............................................................................................2-7
2.5.4
J1850 Communications Controller ............................................................................2-7
2.6
DESIGN CONSIDERATIONS........................................................................................ 2-7
CHAPTER 3
ADDRESS SPACE
3.1
ADDRESS PARTITIONS............................................................................................... 3-1
3.2
REGISTER FILE............................................................................................................ 3-2
3.3
PERIPHERAL SPECIAL-FUNCTION REGISTERS ...................................................... 3-4
3.4
WINDOWING................................................................................................................. 3-6
CHAPTER 4
STANDARD AND PTS INTERRUPTS
4.1
INTERRUPT SOURCES, VECTORS, AND PRIORITIES............................................. 4-1
4.2
INTERRUPT REGISTERS............................................................................................. 4-2
4.2.1
Interrupt Mask Registers ...........................................................................................4-3
4.2.2
Interrupt Pending Registers ......................................................................................4-4
4.2.3
Peripheral Transaction Server Registers ..................................................................4-6
CHAPTER 5
I/O PORTS
5.1
5.2
5.2.1
5.2.2
5.3
I/O PORTS OVERVIEW ................................................................................................ 5-1
INTERNAL STRUCTURE FOR PORTS 1, 2, 5, AND 6 (BIDIRECTIONAL PORTS).... 5-1
Configuring Ports 1, 2, 5, and 6 (Bidirectional Ports) ................................................5-3
Special Bidirectional Port Considerations .................................................................5-4
INTERNAL STRUCTURE FOR PORTS 3 AND 4 (ADDRESS/DATA BUS).................. 5-5