參數(shù)資料
型號: 8XC196LX
英文描述: 8XC196Lx - 8XC196Lx Supplement to 8X196Kx. 8X196Jx. 87C196CA User's Manual
中文描述: 8XC196Lx - 8XC196Lx補編8X196Kx。 8X196Jx。 87C196CA用戶手冊
文件頁數(shù): 63/136頁
文件大?。?/td> 659K
代理商: 8XC196LX
7-5
EVENT PROCESSOR ARRAY
7.1.2
EPA Pending Registers
Figures 7-5 and 7-6 illustrate the EPA pending registers, EPA_PEND and EPA_PEND1, for the
8XC196L
x
microcontroller family.
EPA_PEND
Address:
Reset State:
1FA2H
0000H
When hardware detects a pending EPA
6–9 or OVR0–3, 8–9 interrupt request, it sets the
corresponding bit in the EPA interrupt pending register (EPA_PEND or EPA_PEND1). The EPAIPV
register contains a number that identifies the highest priority, active, shared interrupt source. When
EPAIPV is read, the EPA interrupt pending bit associated with the EPAIPV priority value is cleared.
15
8
Lx
EPA6
EPA7
EPA8
EPA9
OVR0
OVR1
7
0
0VR2
OVR3
OVR8
OVR9
Bit
Number
Function
15:0
Any set bit indicates that the corresponding EPAx interrupt source is pending. The bit is
cleared when software reads the EPA interrupt priority vector register (EPAIPV).
Bits 2–5 and 14–15 are reserved on the 8XC196L
x
device family. For compatibility with future
devices, write zeros to these bits.
Figure 7-5. EPA Interrupt Pending (EPA_PEND) Register
EPA_PEND1
Address:
Reset State:
1FA6H
00H
When hardware detects a pending EPA
x
interrupt, it sets the corresponding bit in the EPA interrupt
pending register (EPA_PEND or EPA_PEND1). The EPAIPV register contains a number that
identifies the highest priority, active, multiplexed interrupt source. When EPAIPV is read, the EPA
interrupt pending bit associated with the EPAIPV priority value is cleared.
7
0
COMP0
COMP1
OVRTM1
OVRTM2
Bit
Number
Function
7:4
Reserved; always write as zeros.
3:0
Any set bit indicates that the corresponding EPAxinterrupt source is pending. The bit is
cleared when the EPA interrupt priority vector register (EPAIPV) is read.
87C196LA, LB only; reserved on 83C196LD.
Figure 7-6. EPA Interrupt Pending 1 (EPA_PEND1) Register
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