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參數(shù)資料
| 型號(hào)： | 8XC196LX |
| 英文描述： | 8XC196Lx - 8XC196Lx Supplement to 8X196Kx. 8X196Jx. 87C196CA User＇s Manual |
| 中文描述： | 8XC196Lx - 8XC196Lx補(bǔ)編8X196Kx。 8X196Jx。 87C196CA用戶手冊(cè) |
| 文件頁數(shù)： | 45/136頁 |
| 文件大?。?/td> | 659K |
| 代理商： | 8XC196LX |
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5-1
CHAPTER 5
I/O PORTS
The I/O ports of the 8XC196L
x
are functionally identical to those of the 8XC196J
x
. However, on
the 87C196LA and LB, the reset state level of all 41 general-purpose I/O pins has changed from
a weak logic “1” (wk1) to a weak logic “0” (wk0). This chapter outlines the differences between
the 87C196LA, LB and the 8XC196K
x
controllers.
5.1
I/O PORTS OVERVIEW
Table 5-1 provides an overview of the 8XC196L
x
and 8XC196K
x
I/O ports.
5.2
INTERNAL STRUCTURE FOR PORTS 1, 2, 5, AND 6 (BIDIRECTIONAL
PORTS)
Figure 5-1 shows the logic for driving the output transistors, Q1 and Q2. Consult the datasheet
for specifications on the amount of current that each port can source or sink.
In I/O mode (selected by clearing a port mode register bit
)
, the port data output and the port di-
rection registers are input to the multiplexers. These signals combine to drive the gates of Q1 and
Q2 so that the output is high, low, or high impedance.
In special-function mode (selected by setting a port mode register bit), SFDIR and SFDATA are
input to the multiplexers. These signals combine to drive the gates of Q1 and Q2 so that the output
is high, low, or high impedance. Special-function output signals clear SFDIR; special-function
Table 5-1. Microcontroller Ports
Port
Pins
Type
Configuration
Options
Associated Peripheral or
System Function
Port 0
8 (Kx)
6 (CA, Jx, Lx)
Standard
Input-only
A/D converter
(not supported on LD)
Port 1
8 (Kx)
4 (CA, Jx, Lx)
Standard
Complementary
Open-drain
EPA and timers
Port 2
8 (Kx)
6 (CA, Jx, Lx)
Standard
Complementary
Open-drain
J1850 (LB only), SIO,
interrupts, bus control, clock
gen.
Port 3
8
Memory mapped
Complementary
Open-drain
Address/data bus
Port 4
8
Memory mapped
Complementary
Open-drain
Address/data bus
Port 5
8 (Kx)
3 (CA, Jx, Lx)
Memory mapped
Complementary
Open-drain
Bus control, slave port
Port 6
8 (Kx)
6 (CA, Jx, Lx)
Standard
Complementary
Open-drain
EPA, SSIO
相關(guān)PDF資料 |
PDF描述 |
|---|---|
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| 8XC51FC | 8-bit CMOS (low voltage, low power and high speed) microcontroller families |
| 8XC51RD | 8-bit CMOS (low voltage, low power and high speed) microcontroller families |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 8XC196MC | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:INDUSTRIAL MOTOR CONTROL MICROCONTROLLER |
| 8XC196MD | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:INDUSTRIAL MOTOR CONTROL MICROCONTROLLER |
| 8XC196MH | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER |
| 8XC196NP | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:COMMERCIAL CHMOS 16-BIT MICROCONTROLLER |
| 8XC196NT | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:CHMOS MICROCONTROLLER WITH 1 MBYTE LINEAR ADDRESS SPACE |
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