參數(shù)資料
型號(hào): 8XC196LX
英文描述: 8XC196Lx - 8XC196Lx Supplement to 8X196Kx. 8X196Jx. 87C196CA User's Manual
中文描述: 8XC196Lx - 8XC196Lx補(bǔ)編8X196Kx。 8X196Jx。 87C196CA用戶手冊(cè)
文件頁(yè)數(shù): 39/136頁(yè)
文件大?。?/td> 659K
代理商: 8XC196LX
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4-5
STANDARD AND PTS INTERRUPTS
INT_PEND
Address:
Reset State:
0009H
00H
When hardware detects an interrupt request, it sets the corresponding bit in the interrupt pending
(INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit.
Software can generate an interrupt by setting the corresponding interrupt pending bit.
7
0
LA
AD
EPA0
EPA1
EPA2
EPA3
EPA
x
7
0
LB
J1850RX
J1850TX
AD
EPA0
EPA1
EPA2
EPA3
EPA
x
7
0
LD
EPA0
EPA1
EPA2
EPA3
EPA
x
Bit
Number
Function
7:0
Any set bit indicates that the corresponding interrupt is pending. The interrupt bit is cleared
when processing transfers to the corresponding interrupt vector.
Bit Mnemonic
Interrupt Description
J1850RX
J1850 Receive (LB only)
J1850TX
J1850 Transmit (LB only)
AD
A/D Conversion Complete (LA, LB)
EPA0
EPA Capture/Compare Channel 0
EPA1
EPA Capture/Compare Channel 1
EPA2
EPA Capture/Compare Channel 2
EPA3
EPA Capture/Compare Channel 3
EPAx
Shared EPA Interrupt
EPA 6–9 capture/compare channel events, EPA 0–1 compare channel events
, EPA
0–3 and 8–9 capture/compare overruns, and timer overflows can generate this shared
interrupt. Write the EPA mask registersto enable the interrupt sources; read the EPA
pending registers to determine which source caused the interrupt.
87C196LA, LB only.
Bits 6–7 are reserved on the 87C196LA, and bits 5–7 are reserved on the 83C196LD. For
compatibility with future devices, write zeros to these bits.
Figure 4-3. Interrupt Pending (INT_PEND) Register
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