IDT EJTAG System
Off-Chip and Probe Interfaces
79RC32438 User Reference Manual
20 - 79
November 4, 2002
Notes
Figure 20.40 System Reset Signal Timing
Voltage Sense for I/O (Vcc I/O) Timing
Figure 20.41 shows the timing for the Vcc I/O signal. Table 20.58 shows the absolute time for the symbol
in the figure. Vcc I/O must rise to the stable level within a specific time T
VIOrise
after the probe detects VccIO
to be above a certain limit T
VIOactive
.
Figure 20.41 Voltage Sense for I/O Signal Timing
The target system must ensure that T
VIOrise
is obeyed after the T
VIOactive
value is reached, so the probe
can use this value to determine when the target has powered-up. The probe is allowed to measure the
T
VIOrise
time from a higher value than T
VIOactive
(but lower than Vcc I/O minimum) because the stable indi-
cation in this case comes later than the time when target power is guaranteed to be stable. If
JTAG_TRST_N is asserted by a pulse at power-up, either on-chip or on PCB, then this reset must be
completed after T
VIOrise
. If JTAG_TRST_N is asserted by a pull-down resistor, then the probe will control
JTAG_TRST_N. At power-down, no power is indicated to the probe when Vcc I/O drops under the T
VIOactive
value, which the probe uses to stop driving the input signals, except for RSTN.
DC Electrical Characteristics
Table 20.59 describes the DC electrical characteristics for voltage and current measured at the probe
connector. Current measures positive in direction from the probe to the target system, and negative in the
other direction. The characteristics apply to the full operating range of the target system.
Symbol
Description
Min.
Max.
Unit
T
RSTNlow
RSTN low time.
1
ms
Table 20.57 System Reset Signal Timing Value
Symbol
Description
Min.
Max.
Unit
T
VIOrise
Vcc I/O rise time from T
VIOactive
to stable Vcc I/O value.
2
sec
Table 20.58 Voltage Sense for I/O Signal Timing Value
RSTN
T
RSTNlow
Driven low
Undriven
tri-stated
Vcc I/O
T
VIOrise
T
VIOactive