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IDT Ethernet Interfaces
Ethernet Register Description
79RC32438 User Reference Manual
11 - 4
November 4, 2002
Notes
0x05_824C through 0x05_FFFF
Reserved
0x06_0000
ETH1INTFC
Ethernet 1 interface control
32-bit
0x06_0004
ETH1FIFOTT
Ethernet 1 FIFO transmit threshold
32-bit
0x06_0008
ETH1ARC
Ethernet 1 address recognition control
32-bit
0x06_000C
ETH1HASH0
Ethernet 1 hash table 0
32-bit
0x06_0010
ETH1HASH1
Ethernet 1 hash table 1
32-bit
0x06_0014 through 0x06_0020
Reserved
0x06_0024
ETH1PFS
Ethernet 1 pause frame status
32-bit
0x06_0028 through 0x6_00FF
Reserved
0x06_0100
ETH1SAL0
Ethernet 1 station address 0 low
32-bit
0x06_0104
ETH1SAH0
Ethernet 1 station address 0 high
32-bit
0x06_0108
ETH1SAL1
Ethernet 1 station address 1 low
32-bit
0x06_010C
ETH1SAH1
Ethernet 1 station address 1 high
32-bit
0x06_0110
ETH1SAL2
Ethernet 1 station address 2 low
32-bit
0x06_0114
ETH1SAH2
Ethernet 1 station address 2 high
32-bit
0x06_0118
ETH1SAL3
Ethernet 1 station address 3 low
32-bit
0x06_011C
ETH1SAH3
Ethernet 1 station address 3 high
32-bit
0x06_0120
ETH1RBC
Ethernet 1 receive byte count
32-bit
0x06_0124
ETH1RPC
Ethernet 1 receive packet count
32-bit
0x06_0128
ETH1RUPC
Ethernet 1 receive undersized packet count
32-bit
0x06_012C
ETH1RFC
Ethernet 1 receive fragment count
32-bit
0x06_0130
ETH1TBC
Ethernet 1 transmit byte count
32-bit
0x06_0134
ETH1GPF
Ethernet 1 generate pause frame
32-bit
0x06_0138 through 0x06_01FF
Reserved
0x06_0200
ETH1MAC1
Ethernet 1 MAC configuration 1
32-bit
0x06_0204
ETH1MAC2
Ethernet 1 MAC configuration 2
32-bit
0x06_0208
ETH1IPGT
Ethernet 1 back-to-back inter-packet gap
32-bit
0x06_020C
ETH1IPGR
Ethernet 1 non back-to-back inter-packet
gap
32-bit
0x06_0210
ETH1CLRT
Ethernet 1 collision window retry
32-bit
0x06_0214
ETH1MAXF
Ethernet 1 maximum frame length
32-bit
0x06_0218
Reserved
0x06_021C
ETH1MTEST
Ethernet 1 MAC test
32-bit
0x06_0220 through 0x06_023C
Reserved
0x06_0240
ETH1CFSA0
Ethernet 1 control frame station address 0
32-bit
Register Offset
1
Register Name
Register Function
Size
Table 11.1 Ethernet Register Map (Part 3 of 4)