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IDT RC32438 Device Overview
RC32438 Internal Register Map
79RC32438 User Reference Manual
1 - 21
November 4, 2002
Notes
RC32438 Internal Register Map
The physical address of a RC32438 internal register is equal to the register offset, shown in Table 1.3,
added to the base value 0x1800_0000. The RC32438 internal register region is not fully decoded.
1
Unless
otherwise noted, all registers should be accessed as aligned 32-bit quantities. Also, all internal registers
should be accessed through non-cacheable addresses.
1.
Addresses for each function may be partitioned into two regions. Region one includes addresses from the start
of the function’s address range to one less than the lowest address that modulo 256 is zero and which is greater
than or equal to the highest defined register for that function. Region two consists of those function addresses not
in region one. For the system identification function, region one would consist of 0x00_0000 through 0x00_00FF
and region two could consist of 0x00_0100 through 0x00_7FFF. Reads from a region one reserved address return
zero. Writes to a region one reserved address are ignored. Reads and writes to region two result in an undecoded
address error. For more information, see the Address Space Monitor section in Chapter 4.
Function
Register Offset
Register
Name
Register Function
System
Identification
0x00_0000 through 0x00_0017
Reserved
0x00_0018
SYSID
System Identification
0x00_001C
Reserved
0x00_0020 through 0x00_7FFF
Reserved
Reset and
Initialization
0x00_8000
RESET
Reset
0x00_8004
BCV
Boot configuration
0x00_8008
1
CEA
CPU error address
Note
: This register can only be
accessed by the CPU. It cannot be
accessed by IPBus masters.
0x00_800C through 0x00_FFFF
Reserved
Device Controller
0x01_0000
DEV0BASE
Device 0 Base
0x01_0004
DEV0MASK
Device 0 Mask
0x01_0008
DEV0C
Device 0 Control
0x01_000C
DEV0TC
Device 0 Timing control
0x01_0010
DEV1BASE
Device 1 Base
0x01_0014
DEV1MASK
Device 1 Mask
0x01_0018
DEV1C
Device 1 Control
0x01_001C
DEV1TC
Device 1 Timing control
0x01_0020
DEV2BASE
Device 2 Base
0x01_0024
DEV2MASK
Device 20 Mask
0x01_0028
DEV2C
Device 2 Control
0x01_002C
DEV2TC
Device 2 Timing control
0x01_0030
DEV3BASE
Device 3 Base
0x01_0034
DEV3MASK
Device 3 Mask
Table 1.3 Internal Register Map (Part 1 of 12)