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型號(hào)：	79RC32V333-133DHI
英文描述：	Microprocessor
中文描述：	微處理器
文件頁(yè)數(shù)：	193/654頁(yè)
文件大?。?/td>	6963K
代理商：	79RC32V333-133DHI

IDT Device Controller

Memory And Peripheral Bus Transaction Timer

79RC32438 User Reference Manual

November 4, 2002

Memory And Peripheral Bus Transaction Timer

When enabled, the memory and peripheral bus transaction timer times all the memory and peripheral

bus transactions. The memory and peripheral bus transaction timer is enabled by setting the bus transac-

tion timer enable (BTE) bit in the BTCS register.

At the start of each memory and peripheral bus transaction in which the bus transaction timer is

enabled, an internal 16-bit counter is initialized to zero. The counter increments with each passing external

clock (EXTCLK) clock cycle until the bus transaction completes. If the counter value ever exceeds the value

in the Compare (COMPARE) field in the Bus Timer Compare (BTCOMPARE) register, then a bus transac-

tion timer time-out occurs.

When the bus transaction timer times-out, the following actions occur:

The bus transaction timer time out (BTO) bit in the BTCS register is set

The address of the transaction which caused the time out is recorded in the bus transaction timer

address (BTADDR) register

The type of bus transaction (i.e., read or write) is recorded in the transaction type (TT) field of the

BTCS register

A warm reset is generated

Compare field is initialized to 0xFFFF and the bus transaction timer is enabled.

Only devices on the memory and peripheral bus with an Intel style wait signal or Motorola style transfer

acknowledge signal can cause the bus transaction timer to time out.

Description:

Write Data Hold.

This field contains the delay, in clock cycles, from when the RC32438 negates

the byte write enable signals during a device write transaction until the buffer output enable

(BOEN) is negated and the data bus (MDATA[15:0]) is tri-stated. Buffer output enable is negated

and the data bus is tri-stated when PWD expires regardless of the value of this field.

Initial Value:

Previous value written

Write Effect:

Modify value

Description:

Chip Select Hold.

This field contains the delay, in clock cycles, from when the RC32438

negates the byte write enable signals during a device write transaction or when output enable is

negated during a device read transaction until the chip select signal is negated. Chip select is

negated when PRD/PWD expires regardless of the value of this field.

Initial Value:

Previous value written

Write Effect:

Modify value

相關(guān)PDF資料	PDF描述
79RC32V333-150DH	8 PIN, 1.75KB, FLASH, 64B RAM, COMPARATOR, 8MHZ INTERNAL OSCILLATOR, -40C to +125C, 8-PDIP, TUBE
79RC32V333-150DHI	Microprocessor
79RC32V334-100BB	MICROPROCESSOR\|32-BIT\|BGA\|256PIN\|PLASTIC
79RC32V334-100BBI	MICROPROCESSOR\|32-BIT\|BGA\|256PIN\|PLASTIC
79RC32V334-133BB	MICROPROCESSOR\|32-BIT\|BGA\|256PIN\|PLASTIC

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
79RC32V333-150DH	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:Microprocessor
79RC32V333-150DHI	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:Microprocessor
79RC32V334-100BB	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:MICROPROCESSOR\|32-BIT\|BGA\|256PIN\|PLASTIC
79RC32V334-100BBG	制造商:Integrated Device Technology Inc 功能描述:MPU RC32300 32-Bit 100MHz 3.3V 256-Pin BGA
79RC32V334-100BBGI	制造商:Integrated Device Technology Inc 功能描述:MPU RC32300 32-Bit 100MHz 3.3V 256-Pin BGA

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