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參數(shù)資料
| 型號： | 24888 |
| 英文描述： | Preliminary AMD-8151 HyperTransport AGP3.0 Graphics Tunnel Data Sheet |
| 中文描述： | 初步的AMD - 8151 HyperTransport的AGP3.0圖形隧道數(shù)據(jù)表 |
| 文件頁數(shù)： | 9/45頁 |
| 文件大小： | 755K |
| 代理商： | 24888 |
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24888 Rev 3.02 - June 17, 2003
AMD-8151
TM
AGP Tunnel Data Sheet
9
The SERR# and PERR# signals are not supported on the AGP bridge.
A_GNT#.
AGP master grant signal.
A_IRDY#.
AGP master ready signal.
A_MB8XDET#.
This pin is controlled by DevA:0x40[8XDIS]. It
is designed to be connected to the AGP connector to indicate
support for AGP 3.0 signaling.
A_PAR.
AGP parity signal.
A_PCLK.
66 MHz AGP clock.
A_PLLCLKO.
PLL clock output. See section 4.3 for details.
A_PLLCLKI.
PLL clock input. See section 4.3 for details.
A_REFCG.
AGP signal reference output.
Output VDD15
IO
Output VDD15
Term
Term
Low
Low
Term
Low
PU
PU
Low
High
PU
Low
VDD15
IO
VDD15
Term
Term
Func.
Func.
PU
Func.
Func.
Low
Func.
Func.
Output VDD33 Func.
Output VDD33 Func.
Input
VDD33
Analog
output
Analog
input
Input
VDD15
Output VDD33
VDD15
A_REFGC.
AGP signal reference input.
VDD15
A_REQ#.
AGP master request signal.
A_RESET#.
AGP bus reset signal. This is asserted whenever
RESET# is asserted or when programmed by
DevB:0x3C[SBRST]. Assertion of this pin does not reset any logic
internal to the IC.
A_RBF#.
AGP read buffer full signal.
A_SBSTB_[P, N].
AGP differential side band address strobe. In
AGP 3.0 signaling mode, A_SBSTB_P is the first strobe and
A_SBSTB_N is the second strobe.
A_SBA[7:0].
AGP side band address signals.
A_ST[2:0].
AGP status signals.
A_STOP#.
AGP target abort signal.
A_TRDY#.
AGP target ready signal.
A_TYPEDET#.
AGP IO voltage level type detect. 0=1.5 volts;
1=3.3 volts (not supported by the IC). The state of this pin is
provided in DevA:0x40[TYPEDET]. This pin is also used for test-
mode selection; see section 9. This signal requires an external
pullup resistor to VDD33 on the systemboard.
A_WBF#.
AGP write buffer full signal.
Term
Low
Term
High
PU
Low
PU
High
Input
Input
VDD15
VDD15
Term
Term
Term
Term
PU
PU
_P: PU
_N: PD
_P: PU
_N: PD
Input
Output VDD15
IO
IO
Input
VDD15
Term
Term
Term
Term
Term
Low
Term
Term
PU
PU
PU
PU
PU
Low
PU
PU
VDD15
VDD15
VDD33
Input
VDD15
Term
Term
PU
PU
Pin name and description
IO cell
type
Power
plane
AGP 3.0
Signaling
During
reset
AGP 2.0
Signaling
During
reset
After
reset
After
reset
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 248-8886-007 | 制造商:ITT Interconnect Solutions 功能描述:248-8886-007 / 248-8886-007 / D Sub |
| 248-8887-007 | 制造商:ITT Interconnect Solutions 功能描述:248-8887-007 / 248-8887-007 / D Sub |
| 248-8888-007 | 制造商:ITT Interconnect Solutions 功能描述:248-8888-007 / 248-8888-007 / D Sub |
| 248-8889-007 | 制造商:ITT Interconnect Solutions 功能描述:248-8889-007 / 248-8889-007 / D Sub |
| 248-8890-007 | 制造商:ITT Interconnect Solutions 功能描述:248-8890-007 / 248-8890-007 / D SUB |
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