參數(shù)資料
型號(hào)： 24888
英文描述： Preliminary AMD-8151 HyperTransport AGP3.0 Graphics Tunnel Data Sheet
中文描述： 初步的AMD - 8151 HyperTransport的AGP3.0圖形隧道數(shù)據(jù)表
文件頁數(shù)： 8/45頁
文件大?。?/td> 755K
代理商： 24888
24888 Rev 3.02 - June 17, 2003
AMD-8151
TM
AGP Tunnel Data Sheet
8
3.3
AGP Signals
In the table below, “Term” indicates the standard AGP 3.0 termination impedance to ground; “PU”
indicates a weak pullup resistor; “PD” indicates a weak pulldown resistor.
Pin name and description
IO cell
type
Power
plane
AGP 3.0
Signaling
During
reset
Term
AGP 2.0
Signaling
During
reset
_P: PU
_N: PD
After
reset
Term
After
reset
_P: PU
_N: PD
A_ADSTB0_[P, N].
AGP differential strobe for A_AD[15:0] and
A_CBE_L[1:0]. When AGP 3.0 signaling is enabled,
A_ADSTB0_P is the first strobe and A_ADSTB0_N is the second
strobe.
A_ADSTB1_[P, N].
AGP differential strobe for AD[31:16],
A_CBE_L[3:2], and A_DBI[H,L]. When AGP 3.0 signaling is
enabled, A_ADSTB1_P is the first strobe and A_ADSTB1_N is
the second strobe.
A_AD[31:0].
AGP address-data bus.
A_CBE_L[3:0].
AGP command-byte enable bus.
A_CAL[D, S] and A_CAL[D, S]#.
Compensation pins for
matching impedance of system board AGP traces. See
DevA:0x[54, 50] for more information. These are designed to be
connected through resistors as follows:
IO
VDD15
IO
VDD15
Term
Term
_P: PU
_N: PD
_P: PU
_N: PD
IO
IO
VDD15
VDD15
Term
Term
Term
Term
PU
PU
Low
Low
Signal
A_CALD
A_CALD# Falling edge of data signals
A_CALS
Rising edge of strobe signals
A_CALS# Falling edge of strobe signals Resistor to VDD15
Compensation Function
Rising edge of data signals
External Connection
Resistor to VSS
Resistor to VDD15
Resistor to VSS
These resistors are used by the compensation circuit. The output of
this circuit is combined with DevA:0x[54, 50] to determine com-
pensation values that are passed to the link PHYs.
A_DBI[H, L].
Data bus inversion [high, low]. When
DevA:0xA4[AGP3MD]=1, A_DBIL applies to AD[15:0];
A_DBIH applies to AD[31:16]. 1=AD signals are inverted.
0=A_AD signals are not inverted. The IC uses these signals in
determining the polarity of the A_AD signals when they are
inputs. These may also be enabled to support the DBI function of
the IC output signals by DevA:0x40[DBIEN]. Both A_DBIH and
A_DBIL are strobed with A_ADSTB1_[P, N].
Analog VDD15
When DevA:0xA4[AGP3MD]=0: A_DBIL is pulled low with the
AGP termination value and not used by the IC; A_DBIH is pulled
up to VDD15 through a weak resistor and becomes the AGP 2.0
PIPE# input signal.
A_DEVSEL#.
AGP device select.
A_FRAME#.
AGP frame signal.
A_GC8XDET#.
0=Specifies that the graphics device supports
AGP 3.0 signaling. The state of this signal is latched on the rising
edge of A_RESET# before being passed to internal logic.
IO
VDD15
Term
Term
PU
PU
IO
IO
Input
w/PU
VDD15
VDD15
VDD15
Term
Term
PU
Term
Term
PU
PU
PU
PU
PU
PU
PU
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