參數(shù)資料
型號(hào)： 24888
英文描述： Preliminary AMD-8151 HyperTransport AGP3.0 Graphics Tunnel Data Sheet
中文描述： 初步的AMD - 8151 HyperTransport的AGP3.0圖形隧道數(shù)據(jù)表
文件頁(yè)數(shù)： 7/45頁(yè)
文件大?。?/td> 755K
代理商： 24888
24888 Rev 3.02 - June 17, 2003
AMD-8151
TM
AGP Tunnel Data Sheet
7
3.2
Tunnel Link Signals
The following are signals associated with the HyperTransport
TM
links. [B, A] in the signal names below refer
to the A and B sides of the tunnel. [P, N] are the positive and negative sides of differential pairs.
Pin name and description
* The signals connected to the A side of the tunnel are powered by VDD12A and the signals connected to the
B side of the tunnel are powered by VDD12B.
** Diff High and Diff Low for these link pins specifies differential high and low; e.g., Diff High specifies that
the _P signal is high and the _N signal is low.
If one of the sides of the tunnel is not used on a platform then the unconnected link should be treated as fol-
lows, for every 10 differential pairs: connect all of the _P differential inputs together and through a resistor to
VSS; connect all the _N differential inputs together and through a resistor to VDD12; leave the differential out-
puts unconnected. If there are unused link signals on an active link (because the IC is connected to a device
with a reduced bit width), then the unused differential inputs and outputs should also be connected in this way.
IO cell
type
Analog VDD-
Power
plane*
During
reset
After
reset
LDTCOMP[3:0].
Link compensation pins for both sides of the tunnel. These are
designed to be connected through resistors as follows:
Bit
[0]
[1]
[3, 2]
Function
Positive receive compensation Resistor to VDD12B
Negative receive compensationResistor to VSS
Transmit compensation
External Connection
Resistor from bit [2] to bit [3]
These resistors are used by the compensation circuit. The output of this circuit is
combined with DevA:0x[E8, E4, E0] to determine compensation values that are
passed to the link PHYs.
LRACAD_[P, N][15:0]; LRBCAD_[P, N][7:0].
Receive link command-address-
data bus.
LRACLK[1, 0]_[P, N]; LRBCLK0_[P, N].
Receive link clock.
12B
Link
input
Link
input
Link
input
Link
output
Link
output
Link
output
VDD12
VDD12
LR[B, A]CTL_[P, N].
Receive link control signal.
VDD12
LTACAD_[P, N][15:0]; LTBCAD_[P, N][7:0].
Transmit link command-address-
data bus.
LTACLK[1, 0]_[P, N]; LTBCLK0_[P, N].
Transmit link clock.
VDD12
Diff
High**
Func.
VDD12 Func.
Func.
LT[B, A]CTL_[P, N].
Transmit link control signal.
VDD12
Diff
Low**
Func.
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