參數(shù)資料
型號: 24888
英文描述: Preliminary AMD-8151 HyperTransport AGP3.0 Graphics Tunnel Data Sheet
中文描述: 初步的AMD - 8151 HyperTransport的AGP3.0圖形隧道數(shù)據(jù)表
文件頁數(shù): 30/45頁
文件大?。?/td> 755K
代理商: 24888
24888 Rev 3.02 - June 17, 2003
AMD-8151
TM
AGP Tunnel Data Sheet
30
5.3
AGP Bridge Configuration Registers
These registers are located in PCI configuration space, in the second device (device B), function 0. See section
5.1.2 for a description of the register naming convention.
AGP Bridge Vendor And Device ID Register
DevB:0x00
Default: 7455 1022h
Bits
Description
31:16
AGP bridge device ID
. Bits[31:20] are read only; bits[19:16] are write-once. When the LSBs are left
at the default value, some operating systems may load a generic graphics driver. System BIOS should
program the LSBs to 6h in order to circumvent the loading of such a driver.
15:0
Vendor ID
. Read only.
Attribute: See below.
AGP Bridge Status And Command Register
DevB:0x04
Default: 0220 0000h
Bits
Description
31:9
Read only. These bits are fixed in their default state.
8
SERREN: SERR# enable.
Read-write. This bit controls no hardware.
7:3
Special cycle enable.
Read only. This bit is hardwired low.
2
MASEN: PCI master enable.
Read-write. 1=Enables the AGP bus master to initiate PCI cycles to
the host.
1
MEMEN: memory enable.
Read-write. 1=Enables access to the AGP bus memory space.
0
IOEN: IO enable.
Read-write. 1=Enables access to the AGP bus IO space.
Attribute: See below.
AGP Bridge Revision and Class Code Register
DevB:0x08
Default: 0604 00h
Bits
Description
31:8
CLASSCODE.
7:0
REVISION.
Attribute: Read only.
AGP Bridge BIST-Header-Latency-Cache Register
DevB:0x0C
Default: 0001 0000h
Bits
Description
31:24
BIST.
Read only. These bits fixed at their default values.
23:16
HEADER.
Read only. These bits fixed at their default values.
Attribute: See below.
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