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| 型號： | 24888 |
| 英文描述： | Preliminary AMD-8151 HyperTransport AGP3.0 Graphics Tunnel Data Sheet |
| 中文描述： | 初步的AMD - 8151 HyperTransport的AGP3.0圖形隧道數(shù)據(jù)表 |
| 文件頁數(shù)： | 10/45頁 |
| 文件大?。?/td> | 755K |
| 代理商： | 24888 |
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24888 Rev 3.02 - June 17, 2003
AMD-8151
TM
AGP Tunnel Data Sheet
10
3.4
Test and Miscellaneous Signals
3.5
Power and Ground
VDD12[B, A].
1.2 volt power plane for the HyperTransport
TM
technology pins. VDD12A provides power to
the A side of the tunnel. VDD12B provides power to the B side of the tunnel.
VDD15.
1.5 volt power plane for AGP.
VDD18.
1.8-volt power plane for the core of the IC.
VDDA18.
Analog 1.8-volt power plane for the PLLs in the core of the IC. This power plane is required to be
filtered from digital noise.
VDD33.
3.3-volt power plane for IO.
VSS.
Ground.
3.5.1
Power Plane Sequencing
The following are power plane requirements that may imply power supply sequencing requirements.
VDD33 is required to always be higher than VDD18, VDDA18, VDD15, and VDD12[B, A].
VDD18 and VDDA18 are required to always be higher than VDD15 and VDD12[B, A].
VDD15 is required to always be higher than VDD12[B, A].
Pin name and description
IO cell
type
Input
Power
plane
VDD33
During
reset
After
reset
CMPOVR.
Link automatic compensation override. 0=Link automatic compensation
is enabled. 1=The compensation values stored in DevA:0x[E0, E4, E8] control the
compensation circuit. The state of this signal determines the default value for
DevA:0x[E0, E4, E8][ACTL and BCTL] at the rising edge of PWROK.
FREE[7:1].
These should be left unconnected.
LDTSTOP#.
Link disconnect control signal. This pin is also used for test-mode
selection; see section 9.
NC[1:0].
These should be left unconnected.
PWROK.
Power OK. 1=All power planes are valid. The rising edge of this signal is
deglitched; it is not observed internally until it is high for more than 6 consecutive
REFCLK cycles. See section 4.2 for more details about this signal.
REFCLK.
66 MHz reference clock. This is required to be operational and valid for a
minimum of 200 microseconds prior to the rising edge of PWROK and always while
PWROK is high.
RESET#.
Reset input. See section 4.2 for details.
STRAPL[19:13, 11:0].
Strapping option to be tied low. These pins should be tied to
ground. STRAPL0 is used for test-mode selection; see section 9.
STRAPL[22:20].
Strapping option to be tied low. These pins should be tied to
ground.
TEST.
This is required to be tied low for functional operation. See section 9 for
details.
Input
VDD33
Input
VDD33
Input
VDD33
Input
IO
VDD33
VDD15 3-State 3-State
IO
VDD33 3-State 3-State
Input
VDD33
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 248-8886-007 | 制造商:ITT Interconnect Solutions 功能描述:248-8886-007 / 248-8886-007 / D Sub |
| 248-8887-007 | 制造商:ITT Interconnect Solutions 功能描述:248-8887-007 / 248-8887-007 / D Sub |
| 248-8888-007 | 制造商:ITT Interconnect Solutions 功能描述:248-8888-007 / 248-8888-007 / D Sub |
| 248-8889-007 | 制造商:ITT Interconnect Solutions 功能描述:248-8889-007 / 248-8889-007 / D Sub |
| 248-8890-007 | 制造商:ITT Interconnect Solutions 功能描述:248-8890-007 / 248-8890-007 / D SUB |
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