參數(shù)資料
型號： 24888
英文描述： Preliminary AMD-8151 HyperTransport AGP3.0 Graphics Tunnel Data Sheet
中文描述： 初步的AMD - 8151 HyperTransport的AGP3.0圖形隧道數(shù)據(jù)表
文件頁數(shù)： 27/45頁
文件大小： 755K
代理商： 24888
24888 Rev 3.02 - June 17, 2003
AMD-8151
TM
AGP Tunnel Data Sheet
27
Link Frequency Capability 0 Register
DevA:0xCC
Default: 0035 0022h.
Bits
Description
31:16
FREQCAPA: link A frequency capability.
Read only. These bits indicate that A side of the tunnel
supports 200, 400, 600, and 800 MHz link frequencies.
15:12 Reserved.
11:8
FREQA: link A frequency.
Read-write. Specifies the link side A frequency. Legal values are 0h (200
MHz), 2h (400 MHz), 4h (600 MHz), and 5h (800 MHz). Note: this bit is cleared by PWROK reset,
not by RESET#. Note: after this field is updated, the link frequency does not change until either
RESET# is asserted or a link disconnect sequence occurs through LDTSTOP#.
7:0
REVISION.
Read only. Revision A of the IC is designed to version 1.02 of the link specification.
Attribute: See below.
Link Frequency Capability 1 Register
DevA:0xD0
Default: 0035 0002h.
Bits
Description
31:16
FREQCAPB: link B frequency capability.
Read only. These bits indicate that that B side of the
tunnel supports 200, 400, 600, and 800 MHz link frequencies.
15:12 Reserved.
11:8
FREQB: link B frequency.
Read-write. Specifies the link side B frequency. Legal values are 0h (200
MHz), and 2h (400 MHz), 4h (600 MHz), and 5h (800 MHz). Note: although it is possible to program
this field for higher frequencies, the B link of the IC is only designed to support 200 and 400 MHz
operation. Note: this bit is cleared by PWROK reset, not by RESET#. Note: after this field is updated,
the link frequency does not change until either RESET# is asserted or a link disconnect sequence
occurs through LDTSTOP#.
7:0
Link device feature capability indicator.
Read only. These bits are set to indicate that the IC
supports LDTSTOP#.
Attribute: See below.
Link Enumeration Scratchpad Register
DevA:0xD4
Default: 0000 0000h.
Bits
Description
31:16 Reserved.
15:0
ESP: enumeration scratchpad.
Read-write. This field controls no hardware within the IC. Note: this
bit is cleared by PWROK reset, not by RESET#.
Attribute: See below.
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相關代理商/技術參數(shù)
參數(shù)描述
248-8886-007 制造商:ITT Interconnect Solutions 功能描述:248-8886-007 / 248-8886-007 / D Sub
248-8887-007 制造商:ITT Interconnect Solutions 功能描述:248-8887-007 / 248-8887-007 / D Sub
248-8888-007 制造商:ITT Interconnect Solutions 功能描述:248-8888-007 / 248-8888-007 / D Sub
248-8889-007 制造商:ITT Interconnect Solutions 功能描述:248-8889-007 / 248-8889-007 / D Sub
248-8890-007 制造商:ITT Interconnect Solutions 功能描述:248-8890-007 / 248-8890-007 / D SUB
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