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| 型號： | 24888 |
| 英文描述： | Preliminary AMD-8151 HyperTransport AGP3.0 Graphics Tunnel Data Sheet |
| 中文描述： | 初步的AMD - 8151 HyperTransport的AGP3.0圖形隧道數(shù)據(jù)表 |
| 文件頁數(shù)： | 16/45頁 |
| 文件大?。?/td> | 755K |
| 代理商： | 24888 |
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24888 Rev 3.02 - June 17, 2003
AMD-8151
TM
AGP Tunnel Data Sheet
16
AGP Device Status And Command Register
DevA:0x04
Default: 0210 0000h
Bits
Description
31
DPE: detected parity error.
Read only. This bit is fixed in the low state.
30
SSE: signaled system error.
Read; set by hardware; write 1 to clear. 1=A system error was signaled
(both links were flooded with sync packets) as a result of a CRC error (see
DevA:0x[C8:C4][CRCFEN, CRCERR]). Note: this bit is cleared by PWROK reset but not by
RESET#.
29
RMA: received master abort.
Read; set by hardware; write 1 to clear. 1=A request (AGP or PCI)
sent to the host bus received a master abort (an NXA error response). Note: this bit is cleared by
PWROK reset but not by RESET#.
28
RTA: received target abort.
Read; set by hardware; write 1 to clear. 1=A request (AGP or PCI) sent
to the host bus received a target abort (a non-NXA error response). Note: this bit is cleared by
PWROK reset but not by RESET#.
27:21 Read only. These bits are fixed in their default state.
20
Capabilities pointer.
Read only. This bit is fixed in the high state.
19:3
Read only. These bits are fixed in their default state.
2
MASEN: PCI master enable.
Read-write. This bit controls no hardware in the IC.
1
MEMEN: memory enable.
Read-write. 1=Enables access to the memory space specified by
DevA:0x10. This bit controls no hardware in the IC.
0
IO enable.
Read only. This bit is fixed in the low state.
Attribute: See below.
AGP Device Revision and Class Code Register
DevA:0x08
Default: 0600 00h
Bits
Description
31:8
CLASSCODE.
Read; write once. Provides the AGP bridge class code.
7:0
REVISION.
Read only.
Attribute: See below.
AGP Device BIST-Header-Latency-Cache Register
DevA:0x0C
Default: 0000 0000h
Bits
Description
31:24
BIST.
These bits fixed at their default values.
23:16
HEADER.
These bits fixed at their default values.
15:8
LATENCY.
These bits fixed at their default values.
7:0
CACHE.
These bits fixed at their default values.
Attribute: Read only.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 249-151 | BEZEICHNUNGSKARTEN 1 BIS 16 |
| 249-152 | BEZEICHNUNGSKARTEN 17 BIS 32 |
| 249-161 | BEZEICHNUNGSSTREIFEN 1 16 |
| 249-162 | BEZEICHNUNGSSTREIFEN RASTER5 17 32 |
| 24919 | Incompatibilities Between the AMD-762? System Controller and the Via Technologies. Inc. VT82C686B |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 248-8886-007 | 制造商:ITT Interconnect Solutions 功能描述:248-8886-007 / 248-8886-007 / D Sub |
| 248-8887-007 | 制造商:ITT Interconnect Solutions 功能描述:248-8887-007 / 248-8887-007 / D Sub |
| 248-8888-007 | 制造商:ITT Interconnect Solutions 功能描述:248-8888-007 / 248-8888-007 / D Sub |
| 248-8889-007 | 制造商:ITT Interconnect Solutions 功能描述:248-8889-007 / 248-8889-007 / D Sub |
| 248-8890-007 | 制造商:ITT Interconnect Solutions 功能描述:248-8890-007 / 248-8890-007 / D SUB |
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