參數(shù)資料
型號(hào)： 24888
英文描述： Preliminary AMD-8151 HyperTransport AGP3.0 Graphics Tunnel Data Sheet
中文描述： 初步的AMD - 8151 HyperTransport的AGP3.0圖形隧道數(shù)據(jù)表
文件頁(yè)數(shù)： 11/45頁(yè)
文件大?。?/td> 755K
代理商： 24888
24888 Rev 3.02 - June 17, 2003
AMD-8151
TM
AGP Tunnel Data Sheet
11
4
Functional Operation
4.1
Overview
The IC connects to the host through either the side A or side B HyperTransport
TM
link interface. The other side
of the tunnel may or may not be connected to another device. Host-initiated transactions that do not target the
IC or the bridge flow through the tunnel to the downstream device. Transactions claimed by the device are
passed to internal registers or to the AGP bridge.
See section 5.1 for details about the software view of the IC. See section 5.1.2 for a description of the register
naming convention. See the AMD-8151
TM
HyperTransport
TM
AGP3.0 Graphics Tunnel Design Guide for addi-
tional information.
4.2
Reset And Initialization
RESET# and PWROK are both required to be low while the power planes to the IC are invalid and for at least
1 millisecond after the power planes are valid. Deassertion of PWROK is referred to as a
cold reset
. After
PWROK is brought high, RESET# is required to stay low for at least 1 additional millisecond. After RESET#
is brought high, the links go through the initialization sequence.
After a cold reset, the IC may be reset by asserting RESET# while PWROK remains high. This is referred to as
a
warm reset
. RESET# must be asserted for no less than 1 millisecond during a warm reset.
4.3
Clocking
It is required that REFCLK be valid in order for the IC to operate. Also, the LR[B, A]CLK inputs from the
operation links must also be valid at the frequency defined DevA:0xCC[FREQA] and DevA:0xD0[FREQB].
The IC provides A_PCLK as the clock to the AGP device.
The systemboard is required to include a connection from A_PLLCLKO to A_PLLCLKI. The length of this
connection is required to be approximately the same as length of the A_PCLK trace from the IC to the external
AGP devices (including approximately 2.5 inches of etch on the AGP card). The IC uses this loopback to help
match the external trace delay.
4.3.1
Clock Gating
Internal clocks may be disabled during power-managed system states such as power-on suspend. It is required
that all upstream requests initiated by the IC be suspended while in this state.
To enable clock gating, DevA:0xF0[ICGSMAF] is programmed to the values in which clock gating will be
enabled. Stop Grant cycles and STPCLK deassertion link broadcasts interact to define the window in which the
IC is enabled for clock gating during LDTSTOP# assertions. The system is placed into power managed states
by steps that include a broadcast over the links of the Stop Grant cycle that includes the System Management
Action Field (SMAF) followed by the assertion of LDTSTOP#. When the IC detects the Stop Grant broadcast
which is enabled for clock gating, it enables clock gating for the next assertion of LDTSTOP#. While exiting
the power-managed state, the system is required to broadcast a STPCLK deassertion message. The IC uses this
message to disable clock gating during LDTSTOP# assertions. This is important because an LDTSTOP# asser-
tion is not guaranteed to occur after the Stop Grant broadcast is received. The clock gating window must be
closed to insure that clock gating does not occur during Stop Grant for LDTSTOP# assertions that are not asso-
相關(guān)PDF資料
PDF描述
249-151 BEZEICHNUNGSKARTEN 1 BIS 16
249-152 BEZEICHNUNGSKARTEN 17 BIS 32
249-161 BEZEICHNUNGSSTREIFEN 1 16
249-162 BEZEICHNUNGSSTREIFEN RASTER5 17 32
24919 Incompatibilities Between the AMD-762? System Controller and the Via Technologies. Inc. VT82C686B
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
248-8886-007 制造商:ITT Interconnect Solutions 功能描述:248-8886-007 / 248-8886-007 / D Sub
248-8887-007 制造商:ITT Interconnect Solutions 功能描述:248-8887-007 / 248-8887-007 / D Sub
248-8888-007 制造商:ITT Interconnect Solutions 功能描述:248-8888-007 / 248-8888-007 / D Sub
248-8889-007 制造商:ITT Interconnect Solutions 功能描述:248-8889-007 / 248-8889-007 / D Sub
248-8890-007 制造商:ITT Interconnect Solutions 功能描述:248-8890-007 / 248-8890-007 / D SUB
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*