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參數(shù)資料
| 型號(hào)： | (Z)PSD813F2 |
| 英文描述： | Flash In System Programmable Mirocomputer Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位和256K位閃速存儲(chǔ)器，16K位SRAM) |
| 中文描述： | Flash在系統(tǒng)可編程Mirocomputer外設(shè)（閃速，在系統(tǒng)可編程微控制器外圍器件，100萬位和256K位閃速存儲(chǔ)器，16K的位的SRAM） |
| 文件頁數(shù)： | 9/32頁 |
| 文件大?。?/td> | 297K |
| 代理商： | (Z)PSD813F2 |
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PSD813FH - 80C31 Design Example …Application Note
052
WSi Inc. Fremont CA 800-832-6974 www.wsipsd.com
9
Control Signal
WRF\
RDF\
A14F
A16F
A17F
A18F
CSF\
Pin (Port) Assignment
20 (PC0)
19 (PC1)
17 (PC3)
14 (PC4)
13 (PC5)
12 (PC6)
11 (PC7)
Table 2 - MCM FLASH die control signals from PSD6XX die
Notice that the address line A15F to the FLASH memory die in Figure 1 is permanently
grounded. This allows the three upper address lines to the FLASH die (A18F, A17F, A16F) to
page through eight segments of FLASH memory, each segment containing 16 Kbytes just like
the monolithic FLASH PSD devices. The lower 14 address lines (A13 - A0) to the FLASH die
address each byte of a particular 16 Kbyte segment.
The special treatment of A14F needs some explanation. Some accesses to the FLASH die
(erasing, writing, identifying, etc.) need to invoke embedded algorithms internal to the FLASH die
as explained in the MCM PSD813FN/FH data sheets. These embedded algorithms are invoked
when the MCU writes special commands to "keyhole" addresses 0x2AAA and 0x5555 on the
FLASH die (note that since A15F is grounded, the aliased addresses 0xAAAA and 0xD555 can
also access embedded algorithms). These addresses require that the address line A14F be
active on the FLASH die. Therefore, during MCU access to the internal FLASH algorithms, the
PSD6XX die will pass MCU address line A14 to the FLASH die address line A14F. When the
MCU reads the FLASH die as it would a ROM, the PSD6XX die will ground address line A14F.
Note: The embedded algorithm "keyhole" addresses for the monolithic FLASH PSD devices
reside at 0xX555 and 0xXAAA to allow greater mapping flexibility (X = don't care).
Let's look at some PSDabel equations used in this design to control the FLASH memory. See
Appendix A for the complete PSDabel source file.
The PSD has four page register bits, pgr0..pgr3, all of which are available to the decoding logic
and programmable logic inside the MCM. This page register is accessible by the 8031 and can
be altered during run-time. Since only four pages of memory are being used in this design, only
two page bits are needed, leaving two bits for other uses.
Here's how the page bits will be used:
page = [pgr1,pgr0]; "PSD page definition
A14F is implemented this way:
pass_a14 = pgr2; "PSD page register bit used to control FLASH algorithm access
a14f = a14 & pass_a14;
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| (Z)PSD813F3R | Multi-Chip-Module to Monolithic Flash PSD(閃速，在系統(tǒng)可編程微控制器外圍器件，0M位閃速存儲(chǔ)器，無SRAM) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZPSD813F2-12JI | 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52 |
| ZPSD813F2-12UI | 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64 |
| ZPSD813F2-15J | 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52 |
| ZPSD813F2-15U | 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64 |
| ZPSD813F2-15UI | 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64 |
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