參數(shù)資料
型號(hào)： (Z)PSD813F2
英文描述： Flash In System Programmable Mirocomputer Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位和256K位閃速存儲(chǔ)器，16K位SRAM)
中文描述： Flash在系統(tǒng)可編程Mirocomputer外設(shè)（閃速，在系統(tǒng)可編程微控制器外圍器件，100萬(wàn)位和256K位閃速存儲(chǔ)器，16K的位的SRAM）
文件頁(yè)數(shù)： 28/32頁(yè)
文件大小： 297K
代理商： (Z)PSD813F2
PSD813FH - 80C31 Design Example …Application Note
052
WSi Inc. Fremont CA 800-832-6974 www.wsipsd.com
28
"Port C pin assignments
"***** These signals are dedicated to controlling the FLASH memory
"***** die in this Multi-chip Module device. These pins can be used
"***** for the JTAG interface on the monolithic part.
"***** The pin at PC2 will accept the backup battery if desired. If
"***** no battery backup SRAM is needed, PC2 should be grounded (MCM
"***** only).
wrf pin 20; "Port C pin pc0, write input to the Flash die
rdf pin 19; "Port C pin pc1, read input to the Flash die
"pc2 is a dedicated pin for Vstby, but the PC2 Output Micro-Cell is
"available for fitting.
a14f pin 17; "Port C pin pc3, flash address pass-though.
"*****Note that address input A15 on the FLASH memory die is grounded
"*****(MCM only).
a16f pin 14; "Port C pin pc4, flash die address
a17f pin 13; "Port C pin pc5, flash die address
a18f pin 12; "Port C pin pc6, flash die address
csf pin 11; "Port C pin pc7, flash die select
"Port D pin assignments
"pd0 is assigned above as the AS input
"clkin pin 9; Port D pin pd1 can be used as a common clock to
"the PLDs and the power down circuitry. If not
"used as a common clock this pin may be used as an
"I/O.
"pd2 pin 8; Port D pin pd2 can be used as I/O or the global
"PSD chip select (CSi). If no equation is written
"for this pin, it must be grounded.
"******** DPLD Outputs and other internal node declaration ********
"***** The following are DPLD outputs (chip selects) for the internal
"***** Boot PROM, SRAM and PSD control registers.
csboot0,csboot1,csboot2,csboot3 node; "Boot PROM segments
rs0, csiop node; "PSD SRAM and PSD control registers
pgr3, pgr2, pgr1, pgr0 node; "PSD internal page register bits.
"Note: Only two bits will be used
"for four pages. pgr2 will be renamed
"as 'pass_a14' and used to implement
"the FLASH memory embedded algorithms.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZPSD813F2-12JI 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
ZPSD813F2-12UI 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64
ZPSD813F2-15J 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
ZPSD813F2-15U 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64
ZPSD813F2-15UI 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64
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