參數(shù)資料
型號(hào)： (Z)PSD813F2
英文描述： Flash In System Programmable Mirocomputer Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位和256K位閃速存儲(chǔ)器，16K位SRAM)
中文描述： Flash在系統(tǒng)可編程Mirocomputer外設(shè)（閃速，在系統(tǒng)可編程微控制器外圍器件，100萬(wàn)位和256K位閃速存儲(chǔ)器，16K的位的SRAM）
文件頁(yè)數(shù)： 30/32頁(yè)
文件大?。?/td> 297K
代理商： (Z)PSD813F2
PSD813FH - 80C31 Design Example …Application Note
052
WSi Inc. Fremont CA 800-832-6974 www.wsipsd.com
30
fs0 = ((address >= ^h8000) & (address <= ^hBFFF) & (page == 3) & !swap)
# ((address >= ^h0000) & (address <= ^h3FFF) & (page == X) & swap);
fs1 = (address >= ^h4000) & (address <= ^h7FFF) & (page == X);
fs2 = (address >= ^h8000) & (address <= ^hBFFF) & (page == 0);
fs3 = (address >= ^hC000) & (address <= ^hFFFF) & (page == 0);
fs4 = (address >= ^h8000) & (address <= ^hBFFF) & (page == 1);
fs5 = (address >= ^hC000) & (address <= ^hFFFF) & (page == 1);
fs6 = (address >= ^h8000) & (address <= ^hBFFF) & (page == 2);
fs7 = (address >= ^hC000) & (address <= ^hFFFF) & (page == 2);
"***** Generate active high chip selects for the boot PROM. csboot0
"***** contains vectors that point to routines in csboot0 and csboot1
"***** for booting and downloading FLASH over the 8031 UART.
csboot0= ((address >= ^h0000) & (address <= ^h1FFF) & (page == X) & !swap);
csboot1= ((address >= ^h2000) & (address <= ^h3FFF) & (page == X) & !swap);
"***** Generate active high chip select for the PSD SRAM. This area
"***** is active on any page and begins at the address just after
"***** the 8031 internal RAM ends. Although the SRAM in this Multichip
"***** Module device is 512 bytes, the Monolithic PSD8XXF device
"***** has 2Kbyte, thus 2K bytes are decoded here.
"***** Note: This address range involves a feedback term in the rs0
"***** equation. Due to the internal architecture of the Multi-chip
"***** Module, this chip select must be routed to a pin on the MCM
"***** and fed back to rs0. This extra step will not be neccessary
"***** on the monolithic PSD8XXF device.
rs0_node = (address >= ^h0100) & (address <= ^h08FF) & (page == X);
rs0 = rs0_node;
"***** Generate active high chip select for the PSD control registers.
"***** These registers are accessible from any page and occupy 256
"***** bytes of address space. Refer to the PSD8XXF data sheet for
"***** register definitions and offsets.
csiop
= (address >= ^h0900) & (address <= ^h09FF) & (page == X);
******** GPLD/ECSPLD Equations ****************************************
"***** Generate the upper memory addresses to FLASH die
a14f = a14 & pass_a14;
"During FLASH writes, a14 is passed through from
"the 8031 to the FLASH die by setting pass_a14 to one.
"This implements the embedded FLASH algorithms
"(access to address 0x2AAA and 0x5555)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZPSD813F2-12JI 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
ZPSD813F2-12UI 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64
ZPSD813F2-15J 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
ZPSD813F2-15U 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64
ZPSD813F2-15UI 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64
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