參數(shù)資料
型號： (Z)PSD813F2
英文描述： Flash In System Programmable Mirocomputer Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位和256K位閃速存儲器，16K位SRAM)
中文描述： Flash在系統(tǒng)可編程Mirocomputer外設(shè)（閃速，在系統(tǒng)可編程微控制器外圍器件，100萬位和256K位閃速存儲器，16K的位的SRAM）
文件頁數(shù)： 10/32頁
文件大?。?/td> 297K
代理商： (Z)PSD813F2
PSD813FH - 80C31 Design Example …Application Note
052
WSi Inc. Fremont CA 800-832-6974 www.wsipsd.com
10
The signal "pass_a14" is set by the MCU before accessing FLASH algorithms. The bit is cleared
by the MCU before the FLASH is used as a ROM.
The "SWAP" bit is implemented this way:
swap = pgr3; "PSD page register bit used to alter the system memory map
The default state of this bit is zero at power-on or PSD reset. When this bit is zero, the system
memory is arranged like that shown in Figure 4 for boot-up and download (if needed).
Afterwards, the 8031 will set SWAP = 1 to convert the system memory map to look like that
shown in Figure 5 for normal operation.
As stated, in this MCM, the PSD die controls the FLASH die by creating signals for the upper
address lines and main chip select. However, the monolithic FLASH PSD will control its main
FLASH memory with eight internal chip selects, fs7 …s0. Even though the MCM does not fit
these chip selects to silicon, equations still need to be written for fs7 …s0. The PSDsoft Address
Translator utility (described later) will use these equations for fs7 …s0 to align the contents of the
MCU firmware file to PSD FLASH memory addresses. Here's what the equations look like for
this MCM design:
fs0 = ((address >= ^h8000) & (address <= ^hBFFF) & (page == 3) & !swap)
# ((address >= ^h0000) & (address <= ^h3FFF) & (page == X) & swap);
fs1 = (address >= ^h4000) & (address <= ^h7FFF) & (page == X);
fs2 = (address >= ^h8000) & (address <= ^hBFFF) & (page == 0);
fs3 = (address >= ^hC000) & (address <= ^hFFFF) & (page == 0);
fs4 = (address >= ^h8000) & (address <= ^hBFFF) & (page == 1);
fs5 = (address >= ^hC000) & (address <= ^hFFFF) & (page == 1);
fs6 = (address >= ^h8000) & (address <= ^hBFFF) & (page == 2);
fs7 = (address >= ^hC000) & (address <= ^hFFFF) & (page == 2);
Note: when this MCM design is converted to a monolithic FLASH PSD design, these equations
for main FLASH memory (fs7 …s0) will be used and no equations for a18f, a17f, a16f, a14f, and
fcs\ will be needed.
Now look at how the three upper address lines (a18f, a17f, a16f) are generated by the PSD6XX
die. Table 3 shows the truth table that we need to implement. Please refer to the memory map in
Figures 4 and 5.
A18F A17F A16F
0
FLASH seg chip
select
fs0
8031 address
range (HEX)
C000
ó
FFFF
or
0000
ó
3FFF
4000
ó
7FFF
PSD Page
Register
3
or
X
X
SWAP
bit
0
or
1
X
0
0
0
0
1
fs1
0
0
1
1
0
1
fs2
fs3
8000
ó
BFFF
C000
ó
FFFF
0
0
X
X
1
1
0
0
0
1
fs4
fs5
8000
ó
BFFF
C000
ó
FFFF
1
1
X
X
1
1
0
fs6
8000
ó
BFFF
2
X
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZPSD813F2-12JI 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
ZPSD813F2-12UI 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64
ZPSD813F2-15J 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
ZPSD813F2-15U 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64
ZPSD813F2-15UI 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64
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