參數(shù)資料
型號: (Z)PSD813F2
英文描述: Flash In System Programmable Mirocomputer Peripherals(閃速,在系統(tǒng)可編程微控制器外圍器件,1M位和256K位閃速存儲器,16K位SRAM)
中文描述: Flash在系統(tǒng)可編程Mirocomputer外設(shè)(閃速,在系統(tǒng)可編程微控制器外圍器件,100萬位和256K位閃速存儲器,16K的位的SRAM)
文件頁數(shù): 1/32頁
文件大?。?/td> 297K
代理商: (Z)PSD813F2
Programmable Peripheral
Application Note 052
PSD813FH - 80C31 Design Example
Multi-Chip-Module to Monolithic Flash
PSD
By Mark Rootz
WSi Inc. Fremont CA 800-832-6974
www.wispsd.com
3/98 Rev 1.0
Introduction
This document will present a FLASH-based embedded microcontroller design that features a
WSi FLASH Programmable System Device (PSD) and an Intel 80C31. The two chips together
serve as an embedded processor core that is an excellent fit for many applications. Issues
associated with downloading and executing code from FLASH memory are simplified.
The 80C31BH-1N is a very inexpensive ROMless microcontroller unit (MCU) that has all the
benefits associated with the support base that exists in the industry for the 8031 family. The WSi
PSD813FH device is a multi-chip module (MCM) that is the first device in a new family of PSDs,
all of which are FLASH-based and In-System-Programmable (ISP). This MCM is pin-for-pin
upward compatible with the low-cost production monolithic FLASH PSD family members, and
can be used for development until the monolithic parts are available. The monolithic parts have
low power features that make this solution an ideal MCU core for compact, low-power, low-cost
applications.
A typical MCU design with FLASH memory consists of the MCU, the main FLASH memory, and
either a boot PROM or SRAM to implement an ISP download to main FLASH memory. For
systems that use SRAM for ISP, the FLASH programming algorithm must first be downloaded to
SRAM and then the MCU executes from SRAM during ISP. Any power interruption or system
glitches that occur will cripple the system. Therefore, a boot PROM is a necessity for applications
that demand high system reliability. However, a boot PROM adds cost to the system and is
difficult to update once in service. FLASH PSDs address these concerns and combine all of the
elements necessary to enable the MCU to easily download main FLASH memory and boot
memory while in circuit (ISP of boot memory available in monolithic devices).
In this MCM design, firmware can be downloaded in-system from a host computer and
programmed into MCM FLASH memory using the MCU's UART channel and the OTP boot code
located in the PSD. This boot code must be programmed by a WSI MagicPro III device
programmer prior to PSD insertion into the circuit. The boot code should contain all of the MCU
routines to access the FLASH as well as handling the UART download protocol from the host
computer.
When the monolithic part is available, all firmware (both boot and main) and PSD configuration
can be downloaded on a completely blank part while in-system using the IEEE 1149.1 JTAG port
Both main and boot firmware can still be downloaded via UART.
You will be taken through this design step-by-step to highlight areas ranging from system design
to device programming. The architecture of this design lays a foundation for an easy transition to
the monolithic FLASH PSD813FX devices.
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參數(shù)描述
ZPSD813F2-12JI 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
ZPSD813F2-12UI 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64
ZPSD813F2-15J 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
ZPSD813F2-15U 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64
ZPSD813F2-15UI 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64