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參數(shù)資料
| 型號： | (Z)PSD813F2 |
| 英文描述： | Flash In System Programmable Mirocomputer Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位和256K位閃速存儲器，16K位SRAM) |
| 中文描述： | Flash在系統(tǒng)可編程Mirocomputer外設（閃速，在系統(tǒng)可編程微控制器外圍器件，100萬位和256K位閃速存儲器，16K的位的SRAM） |
| 文件頁數(shù)： | 7/32頁 |
| 文件大?。?/td> | 297K |
| 代理商： | (Z)PSD813F2 |
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PSD813FH - 80C31 Design Example …Application Note
052
WSi Inc. Fremont CA 800-832-6974 www.wsipsd.com
7
Figure 5 - Memory Map - Normal Operation (SWAP bit = 1)
Here's a top level view of the boot-up sequence:
1. Just after reset, the boot code in ROM segments CSBOOT0 and CSBOOT1
should check to determine if the FLASH memory needs to be programmed
(by checksum test) and also check if there are download requests from the host
computer on the UART channel. Main FLASH memory is in combined data space
and program space at this time (Figure 4).
2. If a download is required, the boot code will facilitate the download by erasing the FLASH,
programming it with data from the UART channel, and verifying the load with a checksum
(Figure 4). Afterwards, execution is transferred from CSBOOT0/CSBOOT1 to the FLASH
memory segment FS1. Executing from FS1, the 8031 will set the "SWAP" bit inside the
PSD, which will remove CSBOOT0/CSBOOT1 and replace it with the FLASH segment
FS0
(Figure 5). Setting the "SWAP" bit also moves all of main FLASH memory to program
space. Normal application code is now in force.
3. If no download is required (FLASH checksum is OK, no host download requests),
execution will jump from CSBOOT0/CSBOOT1 to FS1. From FS1, the 8031 will set the
"SWAP" bit, which puts main FLASH memory in program space, and begins normal
operation.
Note 1: Once the "SWAP" bit is set, the 8031 will have access to 128 Kbytes of FLASH across
three memory pages (see Figure 5).
Note 2: The PSD will power up with the page register = 0.
Note 3: When this MCM design is converted to a monolithic FLASH PSD design, another
download possibility exists. The monolithic devices (PSD813F1/F2/F4) allow ISP of
the boot code as well. Please refer to the section covering Conversion Issues at the
end of this document.
FS1
FS1
FS1
FS1
FS2
FS3
FS4
FS5
FS0
FS6
PAGE 0
PAGE 1
PAGE 2
PAGE 3
COMMON
MEMORY
ACROSS ALL
PAGES
SYSTEM RAM & I/O
FS0
FS0
FS0
FFFF
0000
4000
8000
C000
1000
PAGE X
FFFF
0000
4000
C000
8000
FS7
NOTHING MAPPED
NOTHING MAPPED
NOTHING MAPPED
PROGRAM SPACE (PSEN\)
DATA SPACE (RD\, WR\)
Execute
from
here
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| (Z)PSD813F3R | Multi-Chip-Module to Monolithic Flash PSD(閃速，在系統(tǒng)可編程微控制器外圍器件，0M位閃速存儲器，無SRAM) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZPSD813F2-12JI | 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52 |
| ZPSD813F2-12UI | 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64 |
| ZPSD813F2-15J | 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52 |
| ZPSD813F2-15U | 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64 |
| ZPSD813F2-15UI | 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64 |
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